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Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes:
|
||
|---|---|---|
| .. | ||
| lcdc.c | ||
| Makefile | ||
| simplefb_common.c | ||
| simplefb_common.h | ||
| sunxi_de2.c | ||
| sunxi_display.c | ||
| sunxi_dw_hdmi.c | ||
| sunxi_lcd.c | ||
| tve_common.c | ||