mirror of
https://github.com/AsahiLinux/u-boot
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84335544ea
Add basic support for the Nuvoton NPCM750 EVB (Poleg). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
405 lines
6.4 KiB
Text
405 lines
6.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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/dts-v1/;
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#include "nuvoton-npcm750.dtsi"
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#include "dt-bindings/gpio/gpio.h"
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#include "nuvoton-npcm750-pincfg-evb.dtsi"
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/ {
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model = "Nuvoton npcm750 Development Board (Device Tree)";
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compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
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aliases {
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ethernet2 = &gmac0;
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ethernet3 = &gmac1;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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i2c9 = &i2c9;
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i2c10 = &i2c10;
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i2c11 = &i2c11;
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i2c12 = &i2c12;
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i2c13 = &i2c13;
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i2c14 = &i2c14;
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i2c15 = &i2c15;
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spi0 = &spi0;
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spi1 = &spi1;
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fiu0 = &fiu0;
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fiu1 = &fiu3;
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fiu2 = &fiux;
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};
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chosen {
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stdout-path = &serial0;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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};
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&gmac0 {
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&gmac1 {
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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&fiu0 {
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status = "okay";
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spi-nor@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-rx-bus-width = <2>;
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reg = <0>;
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spi-max-frequency = <5000000>;
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partitions@80000000 {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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bbuboot1@0 {
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label = "bb-uboot-1";
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reg = <0x0000000 0x80000>;
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read-only;
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};
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bbuboot2@80000 {
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label = "bb-uboot-2";
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reg = <0x0080000 0x80000>;
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read-only;
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};
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envparam@100000 {
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label = "env-param";
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reg = <0x0100000 0x40000>;
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read-only;
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};
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spare@140000 {
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label = "spare";
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reg = <0x0140000 0xC0000>;
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};
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kernel@200000 {
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label = "kernel";
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reg = <0x0200000 0x400000>;
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};
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rootfs@600000 {
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label = "rootfs";
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reg = <0x0600000 0x700000>;
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};
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spare1@d00000 {
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label = "spare1";
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reg = <0x0D00000 0x200000>;
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};
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spare2@f00000 {
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label = "spare2";
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reg = <0x0F00000 0x200000>;
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};
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spare3@1100000 {
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label = "spare3";
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reg = <0x1100000 0x200000>;
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};
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spare4@1300000 {
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label = "spare4";
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reg = <0x1300000 0x0>;
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};
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};
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};
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};
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&fiu3 {
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pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
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status = "okay";
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spi-nor@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-rx-bus-width = <2>;
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reg = <0>;
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spi-max-frequency = <5000000>;
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partitions@A0000000 {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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system1@0 {
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label = "spi3-system1";
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reg = <0x0 0x0>;
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};
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};
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};
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};
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&fiux {
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spix-mode;
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};
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&watchdog1 {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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clock-frequency = <24000000>;
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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&adc {
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status = "okay";
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};
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&lpc_kcs {
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kcs1: kcs1@0 {
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status = "okay";
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};
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kcs2: kcs2@0 {
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status = "okay";
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};
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kcs3: kcs3@0 {
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status = "okay";
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};
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};
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/* lm75 on SVB */
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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status = "okay";
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};
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};
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/* lm75 on EB */
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&i2c1 {
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clock-frequency = <100000>;
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status = "okay";
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lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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status = "okay";
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};
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};
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/* tmp100 on EB */
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&i2c2 {
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clock-frequency = <100000>;
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status = "okay";
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tmp100@48 {
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compatible = "tmp100";
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reg = <0x48>;
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status = "okay";
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c5 {
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clock-frequency = <100000>;
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status = "okay";
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};
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/* tmp100 on SVB */
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&i2c6 {
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clock-frequency = <100000>;
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status = "okay";
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tmp100@48 {
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compatible = "tmp100";
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reg = <0x48>;
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status = "okay";
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};
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};
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&i2c7 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c8 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c9 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c10 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c11 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c14 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&pwm_fan {
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status = "okay";
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fan@0 {
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reg = <0x00>;
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fan-tach-ch = /bits/ 8 <0x00 0x01>;
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cooling-levels = <127 255>;
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};
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fan@1 {
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reg = <0x01>;
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fan-tach-ch = /bits/ 8 <0x02 0x03>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@2 {
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reg = <0x02>;
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fan-tach-ch = /bits/ 8 <0x04 0x05>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@3 {
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reg = <0x03>;
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fan-tach-ch = /bits/ 8 <0x06 0x07>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@4 {
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reg = <0x04>;
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fan-tach-ch = /bits/ 8 <0x08 0x09>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@5 {
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reg = <0x05>;
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fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@6 {
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reg = <0x06>;
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fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@7 {
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reg = <0x07>;
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fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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};
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&spi0 {
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cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
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status = "okay";
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Flash@0 {
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compatible = "winbond,w25q128",
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"jedec,spi-nor";
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <5000000>;
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partition@0 {
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label = "spi0_spare1";
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reg = <0x0000000 0x800000>;
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};
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partition@1 {
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label = "spi0_spare2";
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reg = <0x800000 0x0>;
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};
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};
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};
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&spi1 {
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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status = "okay";
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Flash@0 {
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compatible = "winbond,w25q128fw",
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"jedec,spi-nor";
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <5000000>;
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partition@0 {
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label = "spi1_spare1";
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reg = <0x0000000 0x800000>;
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};
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partition@1 {
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label = "spi1_spare2";
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reg = <0x800000 0x0>;
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};
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};
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = < &iox1_pins
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&pin8_input
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&pin9_output_high
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&pin10_input
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&pin11_output_high
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&pin16_input
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&pin24_output_high
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&pin25_output_low
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&pin32_output_high
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&jtag2_pins
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&pin61_output_high
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&pin62_output_high
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&pin63_output_high
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&lpc_pins
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&pin160_input
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&pin162_input
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&pin168_input
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&pin169_input
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&pin170_input
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&pin187_output_high
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&pin190_input
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&pin191_output_high
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&pin192_output_high
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&pin197_output_low
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&ddc_pins
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&pin218_input
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&pin219_output_low
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&pin220_output_low
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&pin221_output_high
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&pin222_input
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&pin223_output_low
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&spix_pins
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&pin228_output_low
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&pin231_output_high
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&pin255_input>;
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};
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