Shengyu Qu 64339bc1f2 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT ... Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-09-05 10:53:46 +08:00
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cpu	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	2023-09-05 10:53:46 +08:00
dts	riscv: jh7110: enable riscv,timer in the device tree	2023-09-05 10:53:36 +08:00
include/asm	cmd/sbi: display new extensions	2023-08-10 10:57:56 +08:00
lib	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE	2023-08-10 10:58:12 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00