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https://github.com/AsahiLinux/u-boot
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ee33f6539d
This patch adds basic support for MediaTek MT8365 SoC. The dtsi has been copied from Linux source code tag v6.7-rc2. (commit 9b5d64654ea8f51fe1e8e29ca1777b620be8fb7c) Signed-off-by: Julien Masson <jmasson@baylibre.com>
840 lines
22 KiB
Text
840 lines
22 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* (C) 2018 MediaTek Inc.
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* Copyright (C) 2022 BayLibre SAS
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* Fabien Parent <fparent@baylibre.com>
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* Bernhard Rosenkränzer <bero@baylibre.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8365-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mediatek,mt8365-power.h>
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/ {
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compatible = "mediatek,mt8365";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-850000000 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <650000>;
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};
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opp-918000000 {
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opp-hz = /bits/ 64 <918000000>;
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opp-microvolt = <668750>;
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};
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opp-987000000 {
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opp-hz = /bits/ 64 <987000000>;
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opp-microvolt = <687500>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <706250>;
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};
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opp-1125000000 {
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opp-hz = /bits/ 64 <1125000000>;
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opp-microvolt = <725000>;
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};
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opp-1216000000 {
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opp-hz = /bits/ 64 <1216000000>;
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opp-microvolt = <750000>;
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};
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opp-1308000000 {
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opp-hz = /bits/ 64 <1308000000>;
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opp-microvolt = <775000>;
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};
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <800000>;
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};
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opp-1466000000 {
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opp-hz = /bits/ 64 <1466000000>;
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opp-microvolt = <825000>;
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};
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opp-1533000000 {
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opp-hz = /bits/ 64 <1533000000>;
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opp-microvolt = <850000>;
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};
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opp-1633000000 {
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opp-hz = /bits/ 64 <1633000000>;
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opp-microvolt = <887500>;
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};
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opp-1700000000 {
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opp-hz = /bits/ 64 <1700000000>;
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opp-microvolt = <912500>;
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};
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opp-1767000000 {
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opp-hz = /bits/ 64 <1767000000>;
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opp-microvolt = <937500>;
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};
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opp-1834000000 {
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opp-hz = /bits/ 64 <1834000000>;
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opp-microvolt = <962500>;
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};
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opp-1917000000 {
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opp-hz = /bits/ 64 <1917000000>;
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opp-microvolt = <993750>;
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};
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opp-2001000000 {
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opp-hz = /bits/ 64 <2001000000>;
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opp-microvolt = <1025000>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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#cooling-cells = <2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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clocks = <&mcucfg CLK_MCU_BUS_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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#cooling-cells = <2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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clocks = <&mcucfg CLK_MCU_BUS_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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#cooling-cells = <2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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clocks = <&mcucfg CLK_MCU_BUS_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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#cooling-cells = <2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2>;
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clocks = <&mcucfg CLK_MCU_BUS_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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idle-states {
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entry-method = "psci";
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CPU_MCDI: cpu-mcdi {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x00010001>;
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entry-latency-us = <300>;
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exit-latency-us = <200>;
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min-residency-us = <1000>;
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};
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CLUSTER_MCDI: cluster-mcdi {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x01010001>;
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entry-latency-us = <350>;
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exit-latency-us = <250>;
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min-residency-us = <1200>;
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};
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CLUSTER_DPIDLE: cluster-dpidle {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x01010004>;
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entry-latency-us = <300>;
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exit-latency-us = <800>;
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min-residency-us = <3300>;
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};
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};
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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-unified;
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};
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};
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clk26m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x10000>, /* GICD */
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<0 0x0c080000 0 0x80000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8365-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt8365-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt8365-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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};
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syscfg_pctl: syscfg-pctl@10005000 {
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compatible = "mediatek,mt8365-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: syscon@10006000 {
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compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
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reg = <0 0x10006000 0 0x1000>;
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#power-domain-cells = <1>;
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/* System Power Manager */
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spm: power-controller {
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compatible = "mediatek,mt8365-power-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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/* power domains of the SoC */
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power-domain@MT8365_POWER_DOMAIN_MM {
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reg = <MT8365_POWER_DOMAIN_MM>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&mmsys CLK_MM_MM_SMI_COMMON>,
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<&mmsys CLK_MM_MM_SMI_COMM0>,
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<&mmsys CLK_MM_MM_SMI_COMM1>,
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<&mmsys CLK_MM_MM_SMI_LARB0>;
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clock-names = "mm", "mm-0", "mm-1",
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"mm-2", "mm-3";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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mediatek,infracfg-nao = <&infracfg_nao>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domain@MT8365_POWER_DOMAIN_CAM {
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reg = <MT8365_POWER_DOMAIN_CAM>;
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clocks = <&camsys CLK_CAM_LARB2>,
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<&camsys CLK_CAM_SENIF>,
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<&camsys CLK_CAMSV0>,
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<&camsys CLK_CAMSV1>,
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<&camsys CLK_CAM_FDVT>,
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<&camsys CLK_CAM_WPE>;
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clock-names = "cam-0", "cam-1",
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"cam-2", "cam-3",
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"cam-4", "cam-5";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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mediatek,smi = <&smi_common>;
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};
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power-domain@MT8365_POWER_DOMAIN_VDEC {
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reg = <MT8365_POWER_DOMAIN_VDEC>;
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#power-domain-cells = <0>;
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mediatek,smi = <&smi_common>;
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};
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power-domain@MT8365_POWER_DOMAIN_VENC {
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reg = <MT8365_POWER_DOMAIN_VENC>;
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#power-domain-cells = <0>;
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mediatek,smi = <&smi_common>;
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};
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power-domain@MT8365_POWER_DOMAIN_APU {
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reg = <MT8365_POWER_DOMAIN_APU>;
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clocks = <&infracfg CLK_IFR_APU_AXI>,
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<&apu CLK_APU_IPU_CK>,
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<&apu CLK_APU_AXI>,
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<&apu CLK_APU_JTAG>,
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<&apu CLK_APU_IF_CK>,
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<&apu CLK_APU_EDMA>,
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<&apu CLK_APU_AHB>;
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clock-names = "apu", "apu-0",
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"apu-1", "apu-2",
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"apu-3", "apu-4",
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"apu-5";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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mediatek,smi = <&smi_common>;
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};
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};
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power-domain@MT8365_POWER_DOMAIN_CONN {
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reg = <MT8365_POWER_DOMAIN_CONN>;
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clocks = <&topckgen CLK_TOP_CONN_32K>,
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<&topckgen CLK_TOP_CONN_26M>;
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clock-names = "conn", "conn1";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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power-domain@MT8365_POWER_DOMAIN_MFG {
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reg = <MT8365_POWER_DOMAIN_MFG>;
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clocks = <&topckgen CLK_TOP_MFG_SEL>;
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clock-names = "mfg";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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power-domain@MT8365_POWER_DOMAIN_AUDIO {
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reg = <MT8365_POWER_DOMAIN_AUDIO>;
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clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
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<&infracfg CLK_IFR_AUDIO>,
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<&infracfg CLK_IFR_AUD_26M_BK>;
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clock-names = "audio", "audio1", "audio2";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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power-domain@MT8365_POWER_DOMAIN_DSP {
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reg = <MT8365_POWER_DOMAIN_DSP>;
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clocks = <&topckgen CLK_TOP_DSP_SEL>,
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<&topckgen CLK_TOP_DSP_26M>;
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clock-names = "dsp", "dsp1";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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};
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt8365-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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};
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8365-apmixedsys", "syscon";
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reg = <0 0x1000c000 0 0x1000>;
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#clock-cells = <1>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt8365-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
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<&infracfg CLK_IFR_PMIC_AP>,
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<&infracfg CLK_IFR_PWRAP_SYS>,
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<&infracfg CLK_IFR_PWRAP_TMR>;
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clock-names = "spi", "wrap", "sys", "tmr";
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};
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keypad: keypad@10010000 {
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compatible = "mediatek,mt6779-keypad";
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reg = <0 0x10010000 0 0x1000>;
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wakeup-source;
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interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
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clocks = <&clk26m>;
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clock-names = "kpd";
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status = "disabled";
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};
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mcucfg: syscon@10200000 {
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compatible = "mediatek,mt8365-mcucfg", "syscon";
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reg = <0 0x10200000 0 0x2000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200a80 0 0x20>;
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};
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iommu: iommu@10205000 {
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compatible = "mediatek,mt8365-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
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mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
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#iommu-cells = <1>;
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};
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infracfg_nao: infracfg@1020e000 {
|
|
compatible = "mediatek,mt8365-infracfg", "syscon";
|
|
reg = <0 0x1020e000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rng: rng@1020f000 {
|
|
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
|
|
reg = <0 0x1020f000 0 0x100>;
|
|
clocks = <&infracfg CLK_IFR_TRNG>;
|
|
clock-names = "rng";
|
|
};
|
|
|
|
apdma: dma-controller@11000280 {
|
|
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
|
|
reg = <0 0x11000280 0 0x80>,
|
|
<0 0x11000300 0 0x80>,
|
|
<0 0x11000380 0 0x80>,
|
|
<0 0x11000400 0 0x80>,
|
|
<0 0x11000580 0 0x80>,
|
|
<0 0x11000600 0 0x80>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
|
dma-requests = <6>;
|
|
clocks = <&infracfg CLK_IFR_AP_DMA>;
|
|
clock-names = "apdma";
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 0>, <&apdma 1>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 2>, <&apdma 3>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@11004000 {
|
|
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
|
reg = <0 0x11004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 4>, <&apdma 5>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@11006000 {
|
|
compatible = "mediatek,mt8365-pwm";
|
|
reg = <0 0x11006000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
|
|
<&infracfg CLK_IFR_PWM>,
|
|
<&infracfg CLK_IFR_PWM1>,
|
|
<&infracfg CLK_IFR_PWM2>,
|
|
<&infracfg CLK_IFR_PWM3>;
|
|
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
|
|
};
|
|
|
|
i2c0: i2c@11007000 {
|
|
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
|
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11008000 {
|
|
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
|
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@11009000 {
|
|
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
|
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@1100a000 {
|
|
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
|
|
reg = <0 0x1100a000 0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg CLK_IFR_SPI0>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@1100f000 {
|
|
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
|
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusb: usb@11201000 {
|
|
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
|
|
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
|
<&u2port1 PHY_TYPE_USB2>;
|
|
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
|
<&infracfg CLK_IFR_SSUSB_REF>,
|
|
<&infracfg CLK_IFR_SSUSB_SYS>,
|
|
<&infracfg CLK_IFR_ICUSB>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usb_host: usb@11200000 {
|
|
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x1000>;
|
|
reg-names = "mac";
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
|
<&infracfg CLK_IFR_SSUSB_REF>,
|
|
<&infracfg CLK_IFR_SSUSB_SYS>,
|
|
<&infracfg CLK_IFR_ICUSB>,
|
|
<&infracfg CLK_IFR_SSUSB_XHCI>;
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck",
|
|
"dma_ck", "xhci_ck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
|
reg = <0 0x11230000 0 0x1000>,
|
|
<0 0x11cd0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
|
|
<&infracfg CLK_IFR_MSDC0_HCLK>,
|
|
<&infracfg CLK_IFR_MSDC0_SRC>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
|
reg = <0 0x11240000 0 0x1000>,
|
|
<0 0x11c90000 0 0x1000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
|
|
<&infracfg CLK_IFR_MSDC1_HCLK>,
|
|
<&infracfg CLK_IFR_MSDC1_SRC>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc2: mmc@11250000 {
|
|
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
|
reg = <0 0x11250000 0 0x1000>,
|
|
<0 0x11c60000 0 0x1000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
|
|
<&infracfg CLK_IFR_MSDC2_HCLK>,
|
|
<&infracfg CLK_IFR_MSDC2_SRC>,
|
|
<&infracfg CLK_IFR_MSDC2_BK>,
|
|
<&infracfg CLK_IFR_AP_MSDC0>;
|
|
clock-names = "source", "hclk", "source_cg",
|
|
"bus_clk", "sys_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet: ethernet@112a0000 {
|
|
compatible = "mediatek,mt8365-eth";
|
|
reg = <0 0x112a0000 0 0x1000>;
|
|
mediatek,pericfg = <&infracfg>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
|
<&infracfg CLK_IFR_NIC_AXI>,
|
|
<&infracfg CLK_IFR_NIC_SLV_AXI>;
|
|
clock-names = "core", "reg", "trans";
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy: t-phy@11cc0000 {
|
|
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x11cc0000 0x9000>;
|
|
|
|
u2port0: usb-phy@0 {
|
|
reg = <0x0 0x400>;
|
|
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
|
<&topckgen CLK_TOP_USB20_48M_EN>;
|
|
clock-names = "ref", "da_ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
u2port1: usb-phy@1000 {
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
|
<&topckgen CLK_TOP_USB20_48M_EN>;
|
|
clock-names = "ref", "da_ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
mmsys: syscon@14000000 {
|
|
compatible = "mediatek,mt8365-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smi_common: smi@14002000 {
|
|
compatible = "mediatek,mt8365-smi-common";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_MM_SMI_COMM0>,
|
|
<&mmsys CLK_MM_MM_SMI_COMM1>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
|
|
};
|
|
|
|
larb0: larb@14003000 {
|
|
compatible = "mediatek,mt8365-smi-larb",
|
|
"mediatek,mt8186-smi-larb";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
|
|
<&mmsys CLK_MM_MM_SMI_LARB0>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
|
|
mediatek,larb-id = <0>;
|
|
};
|
|
|
|
camsys: syscon@15000000 {
|
|
compatible = "mediatek,mt8365-imgsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb2: larb@15001000 {
|
|
compatible = "mediatek,mt8365-smi-larb",
|
|
"mediatek,mt8186-smi-larb";
|
|
reg = <0 0x15001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
|
|
<&camsys CLK_CAM_LARB2>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
|
|
mediatek,larb-id = <2>;
|
|
};
|
|
|
|
vdecsys: syscon@16000000 {
|
|
compatible = "mediatek,mt8365-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb3: larb@16010000 {
|
|
compatible = "mediatek,mt8365-smi-larb",
|
|
"mediatek,mt8186-smi-larb";
|
|
reg = <0 0x16010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&vdecsys CLK_VDEC_LARB1>,
|
|
<&vdecsys CLK_VDEC_LARB1>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
|
|
mediatek,larb-id = <3>;
|
|
};
|
|
|
|
vencsys: syscon@17000000 {
|
|
compatible = "mediatek,mt8365-vencsys", "syscon";
|
|
reg = <0 0x17000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb1: larb@17010000 {
|
|
compatible = "mediatek,mt8365-smi-larb",
|
|
"mediatek,mt8186-smi-larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
|
|
mediatek,larb-id = <1>;
|
|
};
|
|
|
|
apu: syscon@19020000 {
|
|
compatible = "mediatek,mt8365-apu", "syscon";
|
|
reg = <0 0x19020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
system_clk: dummy13m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <13000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
systimer: timer@10017000 {
|
|
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
|
|
reg = <0 0x10017000 0 0x100>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&system_clk>;
|
|
clock-names = "clk13m";
|
|
};
|
|
};
|