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64339bc1f2
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
31 lines
664 B
Text
31 lines
664 B
Text
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2022 StarFive Technology Co., Ltd.
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config STARFIVE_JH7110
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bool
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select ARCH_EARLY_INIT_R
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select CLK_JH7110
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select CPU
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select CPU_RISCV
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select RAM
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select RESET_JH7110
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select SUPPORT_SPL
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select SPL_RAM if SPL
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select SPL_STARFIVE_DDR
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select SYS_CACHE_SHIFT_6
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select SPL_ZERO_MEM_BEFORE_USE
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select PINCTRL_STARFIVE_JH7110
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imply MMC
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imply MMC_BROKEN_CD
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imply MMC_SPI
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SIFIVE_CACHE
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imply SIFIVE_CCACHE
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imply SMP
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imply SPI
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imply SPL_CPU
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imply SPL_LOAD_FIT
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imply SPL_OPENSBI
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imply SPL_RISCV_ACLINT
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imply SPL_SYS_MALLOC_CLEAR_ON_INIT
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