Sagar Shrikant Kadam eb75ee4bd6 riscv: dts: hifive-unleashed-a00: add cpu aliases ... Add cpu aliases to U-Boot specific dtsi for hifive-unleashed. Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 0: cpu@4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>		2020-07-01 15:01:27 +08:00
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ae350_32.dts	riscv: dts: Add #address-cells and #size-cells in nor node	2019-12-10 08:23:10 +08:00
ae350_64.dts	riscv: dts: Add #address-cells and #size-cells in nor node	2019-12-10 08:23:10 +08:00
fu540-c000-u-boot.dtsi	riscv: sifive: dts: fu540: set ethernet clock rate	2020-06-04 09:44:09 +08:00
fu540-c000.dtsi	riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux	2020-06-04 09:44:09 +08:00
fu540-hifive-unleashed-a00-ddr.dtsi	sifive: dts: fu540: Add DDR controller and phy register settings	2020-06-04 09:44:08 +08:00
hifive-unleashed-a00-u-boot.dtsi	riscv: dts: hifive-unleashed-a00: add cpu aliases	2020-07-01 15:01:27 +08:00
hifive-unleashed-a00.dts	riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux	2020-06-04 09:44:09 +08:00
k210-maix-bit.dts	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00
k210.dtsi	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00
Makefile	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00