York Sun eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468 ... Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-10-22 14:31:28 -05:00
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ddr	powerpc/mpc85xx: software workaround for DDR erratum A-004468	2012-10-22 14:31:28 -05:00
cpu.c	powerpc/mpc85xx: Add B4860 and variant SoCs	2012-10-22 14:31:24 -05:00
fdt.c	powerpc/mpc8xxx: Fix USB device-tree fixup	2012-10-22 14:31:12 -05:00
fsl_ifc.c	Added new ext fields to IFC	2012-08-23 12:16:55 -05:00
fsl_lbc.c	fsl_lbc: add printout of LCRR and LBCR to local bus regs	2012-01-13 12:56:06 -06:00
Makefile	powerpc/85xx: Add support for Integrated Flash Controller (IFC)	2011-04-04 09:24:40 -05:00
srio.c	powerpc/mpc85xx: Add T4240 SoC	2012-10-22 14:31:23 -05:00