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af956271f6
The RGMII ports on LS1043ARDB platforms require both RX and TX internal delays to be enabled. The device tree reports only the TX ID because the RX ID used to be enabled by default. With the addition of RX ID support for the Realtek 8211F PHY driver in commite32e4d0f58("net: phy: realtek: add rx delay support for RTL8211F"), the RX ID is disabled by the driver if not reported explicitly. This causes the RX to no longer work. Change the phy-connection-type for the RGMII ports to "rgmii-id" in order to enable both RX and TX internal delays. Fixes:be1d758969("ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB") Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
181 lines
2.9 KiB
Text
181 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright (C) 2015, Freescale Semiconductor
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* Copyright 2020-2021 NXP
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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/dts-v1/;
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/include/ "fsl-ls1043a.dtsi"
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/ {
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model = "LS1043A RDB Board";
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aliases {
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spi1 = &dspi0;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dspiflash: n25q12a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <1000000>; /* input clock */
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};
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};
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&i2c0 {
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status = "okay";
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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eeprom@52 {
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compatible = "at24,24c512";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "at24,24c512";
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reg = <0x53>;
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};
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rtc@68 {
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compatible = "pericom,pt7c4338";
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reg = <0x68>;
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};
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};
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&ifc {
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status = "okay";
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x1 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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nor@0,0 {
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compatible = "cfi-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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cpld: board-control@2,0 {
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compatible = "fsl,ls1043ardb-cpld";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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#include "fsl-ls1043-post.dtsi"
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&fman0 {
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ethernet@e0000 {
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phy-handle = <&qsgmii_phy1>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@e2000 {
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phy-handle = <&qsgmii_phy2>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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status = "okay";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii-id";
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status = "okay";
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};
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ethernet@e8000 {
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phy-handle = <&qsgmii_phy3>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@ea000 {
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phy-handle = <&qsgmii_phy4>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@f0000 { /* 10GEC1 */
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phy-handle = <&aqr105_phy>;
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phy-connection-type = "xgmii";
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status = "okay";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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qsgmii_phy1: ethernet-phy@4 {
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reg = <0x4>;
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};
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qsgmii_phy2: ethernet-phy@5 {
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reg = <0x5>;
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};
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qsgmii_phy3: ethernet-phy@6 {
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reg = <0x6>;
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};
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qsgmii_phy4: ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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mdio@fd000 {
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aqr105_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <0 132 4>;
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reg = <0x1>;
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};
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};
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};
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