mirror of
https://github.com/AsahiLinux/u-boot
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ebe2e0c309
The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project. Signed-off-by: Patrick Wildt <patrick@blueri.se> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Stefano Babic <sbabic@denx.de>
260 lines
6.7 KiB
C
260 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern struct dram_timing_info dram_timing_ch2;
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static void spl_dram_init(void)
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{
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ddr_init(&dram_timing_ch2);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#define USDHC2_VSEL IMX_GPIO_NR(1, 8)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = 1;
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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return ret;
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}
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return 1;
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}
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#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
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PAD_CTL_FSEL2)
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#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
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IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC1_BASE_ADDR, 0, 8},
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{USDHC2_BASE_ADDR, 0, 4},
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};
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int board_mmc_init(struct bd_info *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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*/
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for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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init_clk_usdhc(0);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
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ARRAY_SIZE(usdhc1_pads));
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gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
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gpio_direction_output(USDHC1_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC1_PWR_GPIO, 1);
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break;
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case 1:
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init_clk_usdhc(1);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_request(USDHC2_VSEL, "usdhc2_vsel");
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gpio_direction_output(USDHC2_VSEL, 0);
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break;
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default:
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printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
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#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
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#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
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#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
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#define I2C_MUX_ADDR 0x70
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#define I2C_FAN53555_ADDR 0x60
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static iomux_v3_cfg_t const power_pads[] = {
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IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
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};
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int power_init_board(void)
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{
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uint8_t val;
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imx_iomux_v3_setup_multiple_pads(power_pads,
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ARRAY_SIZE(usdhc2_pads));
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/* Release I2C multiplexer reset */
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gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
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gpio_direction_output(I2C1_PCA9546_RESET, 1);
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/* Select VSEL0 on voltage regulators */
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gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
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gpio_direction_output(ARM_DRAM_VSEL, 0);
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gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
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gpio_direction_output(DRAM_1P1_VSEL, 0);
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gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
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gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
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/* Set mux to target ARM/DRAM regulator */
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i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
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/* .6 + .40 = 1.00 */
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val = 0x80 + 40;
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i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
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i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
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/* Set mux to target DRAM regulator */
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i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
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/* .6 + .50 = 1.10 */
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val = 0x80 + 50;
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i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
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i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
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/* Set mux to target SoC/GPU/VPU regulator */
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i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
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/* .6 + .30 = .90 */
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val = 0x80 + 30;
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i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
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i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
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/* Set mux to target peripherals */
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i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
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return 0;
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}
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void spl_board_init(void)
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{
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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arch_cpu_init();
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init_uart_clk(0);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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