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e9dfd8e960
Previously we have known that R40 has a configuration register for its rank 1, which allows different configuration than rank 0. Reverse engineering of newest libdram of A64 from Allwinner shows that A64 has this register too. It's bit 0 (which enables dual rank in rank 0 configuration register) means a dedicated rank size setup is used for rank 1. Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank DRAM support necessary. Add this support. The code could support both A64 and R40, but because dual rank detection is broken on R40 now, we cannot really use it on R40 currently. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| dram_timings | ||
| board.c | ||
| clock.c | ||
| clock_sun4i.c | ||
| clock_sun6i.c | ||
| clock_sun8i_a83t.c | ||
| clock_sun9i.c | ||
| clock_sun50i_h6.c | ||
| cpu_info.c | ||
| dram_helpers.c | ||
| dram_sun4i.c | ||
| dram_sun6i.c | ||
| dram_sun8i_a23.c | ||
| dram_sun8i_a33.c | ||
| dram_sun8i_a83t.c | ||
| dram_sun9i.c | ||
| dram_sun50i_h6.c | ||
| dram_sun50i_h616.c | ||
| dram_sunxi_dw.c | ||
| gtbus_sun9i.c | ||
| Kconfig | ||
| Makefile | ||
| p2wi.c | ||
| pinmux.c | ||
| pmic_bus.c | ||
| prcm.c | ||
| rmr_switch.S | ||
| rsb.c | ||
| spl_spi_sunxi.c | ||