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https://github.com/AsahiLinux/u-boot
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c1f09505d5
/soc@0 aips1 aips2 aips3 clk iomuxc osc_24m are common node enablements across imx8mm platform for dm-spi, dm-pre-reloc stages. Move them into common dtsi, imx8mm-u-boot.dtsi Cc: Tim Harvey <tharvey@gateworks.com> Cc: Adam Ford <aford173@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
72 lines
780 B
Text
72 lines
780 B
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Gateworks Corporation
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*/
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#include "imx8mm-u-boot.dtsi"
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart2 {
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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u-boot,dm-spl;
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};
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&usdhc3 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc3 {
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u-boot,dm-spl;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&pinctrl_i2c1 {
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u-boot,dm-spl;
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};
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&i2c2 {
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u-boot,dm-spl;
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};
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&pinctrl_i2c2 {
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u-boot,dm-spl;
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};
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&fec1 {
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phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <1>;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
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u-boot,dm-spl;
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};
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