mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 00:33:06 +00:00
35d48ea8c0
There is an existing CONFIG_MCFTMR Kconfig symbol,
use it and drop all other instances of CFG_MCFTMR.
This duality is likely a result of bogus conversion
to Kconfig.
Fixes: 7ff7b46e6c ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Sysam AMCORE board configuration
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*
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* (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
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*/
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#ifndef __AMCORE_CONFIG_H
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#define __AMCORE_CONFIG_H
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#define CFG_SYS_UART_PORT 0
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#define CFG_SYS_UART_PORT 0
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#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_EXTRA_ENV_SETTINGS \
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"upgrade_uboot=loady; " \
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"protect off 0xffc00000 0xffc2ffff; " \
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"erase 0xffc00000 0xffc2ffff; " \
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"cp.b 0x20000 0xffc00000 ${filesize}\0" \
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"upgrade_kernel=loady; " \
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"erase 0xffc30000 0xffefffff; " \
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"cp.b 0x20000 0xffc30000 ${filesize}\0" \
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"upgrade_jffs2=loady; " \
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"erase 0xfff00000 0xffffffff; " \
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"cp.b 0x20000 0xfff00000 ${filesize}\0"
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#define CFG_SYS_CLK 45000000
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#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2)
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/* Register Base Addrs */
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#define CFG_SYS_MBAR 0x10000000
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/* Definitions for initial stack pointer and data area (in DPRAM) */
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#define CFG_SYS_INIT_RAM_ADDR 0x20000000
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/* size of internal SRAM */
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#define CFG_SYS_INIT_RAM_SIZE 0x1000
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#define CFG_SYS_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_SIZE 0x1000000
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#define CFG_SYS_FLASH_BASE 0xffc00000
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/* amcore design has flash data bytes wired swapped */
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#define CFG_SYS_WRITE_SWAPPED_DATA
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text*);
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/* memory map space for linux boot data */
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#define CFG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* Cache Configuration
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*
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* Special 8K version 3 core cache.
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* This is a single unified instruction/data cache.
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* sdram - single region - no masks
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*/
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#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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CFG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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CFG_SYS_INIT_RAM_SIZE - 4)
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#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
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#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
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CF_ACR_EN)
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#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
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CF_CACR_EC)
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/* CS0 - AMD Flash, address 0xffc00000 */
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#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16)
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/* 4MB, AA=0,V=1 C/I BIT for errata */
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#define CFG_SYS_CS0_MASK 0x003f0001
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/* WS=10, AA=1, PS=16bit (10) */
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#define CFG_SYS_CS0_CTRL 0x1980
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/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
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#define CFG_SYS_CS1_BASE 0x3000
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#define CFG_SYS_CS1_MASK 0x00070001
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#define CFG_SYS_CS1_CTRL 0x0100
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#endif /* __AMCORE_CONFIG_H */
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