u-boot/arch/riscv/lib/sifive_clint.c
Sean Anderson e5ca9a7523 riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.

Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.

Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-09-30 08:54:46 +08:00

97 lines
2 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*
* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
* The CLINT block holds memory-mapped control and status registers
* associated with software and timer interrupts.
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
#include <asm/syscon.h>
#include <linux/err.h>
/* MSIP registers */
#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
/* mtime compare register */
#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
/* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
DECLARE_GLOBAL_DATA_PTR;
int riscv_init_ipi(void)
{
int ret;
struct udevice *dev;
ret = uclass_get_device_by_driver(UCLASS_TIMER,
DM_GET_DRIVER(sifive_clint), &dev);
if (ret)
return ret;
gd->arch.clint = dev_read_addr_ptr(dev);
if (!gd->arch.clint)
return -EINVAL;
return 0;
}
int riscv_send_ipi(int hart)
{
writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
}
int riscv_clear_ipi(int hart)
{
writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
}
int riscv_get_ipi(int hart, int *pending)
{
*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
}
static int sifive_clint_get_count(struct udevice *dev, u64 *count)
{
*count = readq((void __iomem *)MTIME_REG(dev->priv));
return 0;
}
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};
static int sifive_clint_probe(struct udevice *dev)
{
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
return timer_timebase_fallback(dev);
}
static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0" },
{ }
};
U_BOOT_DRIVER(sifive_clint) = {
.name = "sifive_clint",
.id = UCLASS_TIMER,
.of_match = sifive_clint_ids,
.probe = sifive_clint_probe,
.ops = &sifive_clint_ops,
.flags = DM_FLAG_PRE_RELOC,
};