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96 lines
3 KiB
C
96 lines
3 KiB
C
/*
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* linux/include/asm-arm/arch-netarm/netarm_registers.h
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*
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* Copyright (C) 2005
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* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
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*
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* Copyright (C) 2000, 2001 NETsilicon, Inc.
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* Copyright (C) 2000, 2001 WireSpeed Communications Corporation
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*
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* This software is copyrighted by WireSpeed. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall WireSpeed
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : Joe deBlaquiere
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*
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* Modified to support NS7520 by Art Shipkowski.
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*/
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#ifndef __NET_ARM_REGISTERS_H
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#define __NET_ARM_REGISTERS_H
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#include <config.h>
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/* fundamental constants : */
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/* the input crystal/clock frequency ( in Hz ) */
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#define NETARM_XTAL_FREQ_25MHz (18432000)
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#define NETARM_XTAL_FREQ_33MHz (23698000)
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#define NETARM_XTAL_FREQ_48MHz (48000000)
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#define NETARM_XTAL_FREQ_55MHz (55000000)
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#define NETARM_XTAL_FREQ_EMLIN1 (20000000)
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/* the frequency of SYS_CLK */
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#if defined(CONFIG_NETARM_EMLIN)
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/* EMLIN board: 33 MHz (exp.) */
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#define NETARM_PLL_COUNT_VAL 6
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
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#elif defined(CONFIG_NETARM_NET40_REV2)
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/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */
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#define NETARM_PLL_COUNT_VAL 6
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
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#elif defined(CONFIG_NETARM_NET40_REV4)
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/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
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NETARM_XTAL_FREQ_25MHz) 4 */
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#define NETARM_PLL_COUNT_VAL 4
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
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#elif defined(CONFIG_NETARM_NET50)
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/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
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#define NETARM_PLL_COUNT_VAL 8
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
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#else /* CONFIG_NETARM_NS7520 */
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#define NETARM_PLL_COUNT_VAL 0
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#if defined(CONFIG_BOARD_UNC20)
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz
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#else
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#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz
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#endif
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#endif
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/* #include "arm_registers.h" */
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#include <asm/arch/netarm_gen_module.h>
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#include <asm/arch/netarm_mem_module.h>
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#include <asm/arch/netarm_ser_module.h>
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#include <asm/arch/netarm_eni_module.h>
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#include <asm/arch/netarm_dma_module.h>
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#include <asm/arch/netarm_eth_module.h>
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#endif
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