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Add support for NetSilicon NS7520 processor.

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Patch by Art Shipkowski, 12 May 2005

Cleanup.
This commit is contained in:
Wolfgang Denk 2005-10-09 01:41:48 +02:00
parent 7521af1c7d
commit 3df5bea0b0
19 changed files with 3290 additions and 1949 deletions
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7
CHANGELOG
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@ -2,6 +2,11 @@
Changes for U-Boot 1.1.4:
======================================================================
* Cleanup
* Add support for NetSilicon NS7520 processor.
Patch by Art Shipkowski, 12 May 2005
* Add support for AP1000 board.
Patch by James MacAulay, 07 Oct 2005
@ -15,7 +20,7 @@ Changes for U-Boot 1.1.4:
issue - the table is aligned on a PAGE_SIZE (4096) boundary).
* Fixed compilation for ARM when using a (standard) hard-FP toolchain
Patch by Anders Larsen, 07 Oct 2005
Patch by Anders Larsen, 07 Oct 2005
* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
sed the linker scripts, rather than pre-process them.

4
CREDITS
View file

@ -377,6 +377,10 @@ N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board

4
README
View file

@ -297,9 +297,9 @@ The following options need to be configured:
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT
CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900
CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA
CONFIG_FPS850L CONFIG_OXC
CONFIG_FPS850L CONFIG_OXC
CONFIG_FPS860L CONFIG_PCI405
ARM based boards:
-----------------

1047
board/amirix/ap1000/ap1000.c
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156
board/amirix/ap1000/ap1000.h
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@ -20,22 +20,22 @@
*/
#define AP1xx_FPGA_REV_ADDR 0x29000000
#define AP1xx_PLATFORM_MASK 0xFF000000
#define AP100_BASELINE_PLATFORM 0x01000000
#define AP1xx_QUADGE_PLATFORM 0x02000000
#define AP1xx_MGT_REF_PLATFORM 0x03000000
#define AP1xx_STANDARD_PLATFORM 0x04000000
#define AP1xx_DUAL_PLATFORM 0x05000000
#define AP1xx_PLATFORM_MASK 0xFF000000
#define AP100_BASELINE_PLATFORM 0x01000000
#define AP1xx_QUADGE_PLATFORM 0x02000000
#define AP1xx_MGT_REF_PLATFORM 0x03000000
#define AP1xx_STANDARD_PLATFORM 0x04000000
#define AP1xx_DUAL_PLATFORM 0x05000000
#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
#define AP1000_BASELINE_PLATFORM 0x21000000
#define AP1xx_TESTPLATFORM_MASK 0xC0000000
#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
#define AP1xx_TESTPLATFORM_MASK 0xC0000000
#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
#define AP1xx_TARGET_MASK 0x00FF0000
#define AP1xx_AP107_TARGET 0x00010000
@ -46,18 +46,18 @@
#define AP1xx_UNKNOWN_STR "Unknown"
#define AP1xx_PLATFORM_STR " Platform"
#define AP1xx_PLATFORM_STR " Platform"
#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
#define AP1xx_STANDARD_PLATFORM_STR "Standard"
#define AP1xx_DUAL_PLATFORM_STR "Dual"
#define AP1xx_DUAL_PLATFORM_STR "Dual"
#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
#define AP1xx_TESTPLATFORM_STR " Test Platform"
#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
#define AP1xx_TESTPLATFORM_STR " Test Platform"
#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
#define AP1xx_TARGET_STR " Board"
#define AP1xx_AP107_TARGET_STR "AP107"
@ -78,84 +78,84 @@
*/
#define AP1000_SYSACE_REGBASE 0x28000000
#define SYSACE_STATREG0 0x04 // 7:0
#define SYSACE_STATREG1 0x05 // 15:8
#define SYSACE_STATREG2 0x06 // 23:16
#define SYSACE_STATREG3 0x07 // 31:24
#define SYSACE_STATREG0 0x04 /* 7:0 */
#define SYSACE_STATREG1 0x05 /* 15:8 */
#define SYSACE_STATREG2 0x06 /* 23:16 */
#define SYSACE_STATREG3 0x07 /* 31:24 */
#define SYSACE_ERRREG0 0x08 // 7:0
#define SYSACE_ERRREG1 0x09 // 15:8
#define SYSACE_ERRREG2 0x0a // 23:16
#define SYSACE_ERRREG3 0x0b // 31:24
#define SYSACE_ERRREG0 0x08 /* 7:0 */
#define SYSACE_ERRREG1 0x09 /* 15:8 */
#define SYSACE_ERRREG2 0x0a /* 23:16 */
#define SYSACE_ERRREG3 0x0b /* 31:24 */
#define SYSACE_CTRLREG0 0x18 // 7:0
#define SYSACE_CTRLREG1 0x19 // 15:8
#define SYSACE_CTRLREG2 0x1A // 23:16
#define SYSACE_CTRLREG3 0x1B // 31:24
#define SYSACE_CTRLREG0 0x18 /* 7:0 */
#define SYSACE_CTRLREG1 0x19 /* 15:8 */
#define SYSACE_CTRLREG2 0x1A /* 23:16 */
#define SYSACE_CTRLREG3 0x1B /* 31:24 */
/*
* Software reconfig thing
*/
#define SW_BYTE_SECTOR_ADDR 0x24FE0000
#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
#define SW_BYTE_SECTOR_SIZE 0x00020000
#define SW_BYTE_MASK 0x00000003
#define SW_BYTE_SECTOR_ADDR 0x24FE0000
#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
#define SW_BYTE_SECTOR_SIZE 0x00020000
#define SW_BYTE_MASK 0x00000003
#define DEFAULT_TEMP_ADDR 0x00100000
#define DEFAULT_TEMP_ADDR 0x00100000
#define AP1000_CPLD_BASE 0x26000000
#define AP1000_CPLD_BASE 0x26000000
/* PowerSpan II Stuff */
#define PSII_SYNC() asm("eieio")
#define PSPAN_BASEADDR 0x30000000
#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
0x00, /* Byte 15 - Vital Product Data Disabled. */ \
0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
0x00, /* Byte 18 - I2O disabled */ \
0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
/* Long Load Information */ \
0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
0x01, /* Byte 39 - Power span revision 1. */ \
0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
0x01, /* Byte 59 - PCI-2 class revision 1 */ \
0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
0x00, /* Byte 15 - Vital Product Data Disabled. */ \
0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
0x00, /* Byte 18 - I2O disabled */ \
0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
/* Long Load Information */ \
0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
0x01, /* Byte 39 - Power span revision 1. */ \
0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
0x01, /* Byte 59 - PCI-2 class revision 1 */ \
0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
#define EEPROM_LENGTH 64 /* Long Load */
#define EEPROM_LENGTH 64 /* Long Load */
#define I2C_SENSOR_DEV 0x9
#define I2C_SENSOR_DEV 0x9
#define I2C_SENSOR_CHIP_SEL 0x4
/*

1154
board/amirix/ap1000/flash.c
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File diff suppressed because it is too large Load diff

8
board/amirix/ap1000/init.S
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@ -25,10 +25,10 @@
#include <asm/mmu.h>
.globl ext_bus_cntlr_init
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
blr
.globl sdram_init
.globl sdram_init
sdram_init:
blr
blr

346
board/amirix/ap1000/pci.c
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@ -30,105 +30,121 @@
#define PCI_IO_82559ER_CSR_BASE 0x40000200
/** AP1100 specific values */
#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
/* static int G_verbosity_level = 1; */
#define G_verbosity_level 1
void write1(unsigned long addr, unsigned char val) {
volatile unsigned char* p = (volatile unsigned char*)addr;
void write1 (unsigned long addr, unsigned char val)
{
volatile unsigned char *p = (volatile unsigned char *) addr;
if(G_verbosity_level > 1)
printf("write1: addr=%08x val=%02x\n", (unsigned int)addr, val);
*p = val;
asm("eieio");
if (G_verbosity_level > 1)
printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
val);
*p = val;
asm ("eieio");
}
unsigned char read1(unsigned long addr) {
unsigned char val;
volatile unsigned char* p = (volatile unsigned char*)addr;
unsigned char read1 (unsigned long addr)
{
unsigned char val;
volatile unsigned char *p = (volatile unsigned char *) addr;
if(G_verbosity_level > 1)
printf("read1: addr=%08x ", (unsigned int)addr);
val = *p;
asm("eieio");
if(G_verbosity_level > 1)
printf("val=%08x\n", val);
return val;
if (G_verbosity_level > 1)
printf ("read1: addr=%08x ", (unsigned int) addr);
val = *p;
asm ("eieio");
if (G_verbosity_level > 1)
printf ("val=%08x\n", val);
return val;
}
void write2(unsigned long addr, unsigned short val) {
volatile unsigned short* p = (volatile unsigned short*)addr;
void write2 (unsigned long addr, unsigned short val)
{
volatile unsigned short *p = (volatile unsigned short *) addr;
if(G_verbosity_level > 1)
printf("write2: addr=%08x val=%04x -> *p=%04x\n", (unsigned int)addr, val,
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
if (G_verbosity_level > 1)
printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
(unsigned int) addr, val,
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm("eieio");
*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm ("eieio");
}
unsigned short read2(unsigned long addr) {
unsigned short val;
volatile unsigned short* p = (volatile unsigned short*)addr;
unsigned short read2 (unsigned long addr)
{
unsigned short val;
volatile unsigned short *p = (volatile unsigned short *) addr;
if(G_verbosity_level > 1)
printf("read2: addr=%08x ", (unsigned int)addr);
val = *p;
val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm("eieio");
if(G_verbosity_level > 1)
printf("*p=%04x -> val=%04x\n",
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
return val;
if (G_verbosity_level > 1)
printf ("read2: addr=%08x ", (unsigned int) addr);
val = *p;
val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm ("eieio");
if (G_verbosity_level > 1)
printf ("*p=%04x -> val=%04x\n",
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
return val;
}
void write4(unsigned long addr, unsigned long val) {
volatile unsigned long* p = (volatile unsigned long*)addr;
void write4 (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if(G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x -> *p=%08x\n", (unsigned int)addr, (unsigned int)val,
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)));
if (G_verbosity_level > 1)
printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
(unsigned int) addr, (unsigned int) val,
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)));
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm("eieio");
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm ("eieio");
}
unsigned long read4(unsigned long addr) {
unsigned long val;
volatile unsigned long* p = (volatile unsigned long*)addr;
unsigned long read4 (unsigned long addr)
{
unsigned long val;
volatile unsigned long *p = (volatile unsigned long *) addr;
if(G_verbosity_level > 1)
printf("read4: addr=%08x", (unsigned int)addr);
if (G_verbosity_level > 1)
printf ("read4: addr=%08x", (unsigned int) addr);
val = *p;
val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm("eieio");
val = *p;
val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm ("eieio");
if(G_verbosity_level > 1)
printf("*p=%04x -> val=%04x\n",
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)), (unsigned int)val);
return val;
if (G_verbosity_level > 1)
printf ("*p=%04x -> val=%04x\n",
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)),
(unsigned int) val);
return val;
}
void write4be(unsigned long addr, unsigned long val) {
volatile unsigned long* p = (volatile unsigned long*)addr;
void write4be (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if(G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x\n", (unsigned int)addr, (unsigned int)val);
*p = val;
asm("eieio");
if (G_verbosity_level > 1)
printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
(unsigned int) val);
*p = val;
asm ("eieio");
}
/** One byte configuration write on PSII.
@ -140,21 +156,14 @@ void write4be(unsigned long addr, unsigned long val) {
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 *val)
static int psII_read_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read1(PSII_CONFIG_DATA+(reg&0x03));
return(0);
*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
}
/** One byte configuration write on PSII.
@ -166,22 +175,15 @@ static int psII_read_config_byte(
* @param val Output byte.
* @return Always Zero.
*/
static int psII_write_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 val)
static int psII_write_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write1(PSII_CONFIG_DATA+(reg&0x03),(unsigned char )val);
write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
return(0);
return (0);
}
/** One word (16 bit) configuration read on PSII.
@ -193,21 +195,14 @@ static int psII_write_config_byte(
* @param val Address of location for received word.
* @return Always Zero.
*/
static int psII_read_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 *val)
static int psII_read_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read2(PSII_CONFIG_DATA+(reg&0x03));
return(0);
*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
}
/** One word (16 bit) configuration write on PSII.
@ -219,22 +214,15 @@ static int psII_read_config_word(
* @param val Output word.
* @return Always Zero.
*/
static int psII_write_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 val)
static int psII_write_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write2(PSII_CONFIG_DATA+(reg&0x03),(unsigned short )val);
write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
return(0);
return (0);
}
/** One DWord (32 bit) configuration read on PSII.
@ -246,21 +234,14 @@ static int psII_write_config_word(
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_dword(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u32 *val)
static int psII_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int reg, u32 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read4(PSII_CONFIG_DATA);
return(0);
*val = read4 (PSII_CONFIG_DATA);
return (0);
}
/** One DWord (32 bit) configuration write on PSII.
@ -272,75 +253,66 @@ static int psII_read_config_dword(
* @param val Output Dword.
* @return Always Zero.
*/
static int psII_write_config_dword(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u32 val)
static int psII_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int reg, u32 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4(PSII_CONFIG_DATA,(unsigned long)val);
write4 (PSII_CONFIG_DATA, (unsigned long) val);
return(0);
return (0);
}
static struct pci_config_table ap1000_config_table[] = {
static struct pci_config_table ap1000_config_table[] = {
#ifdef CONFIG_AP1000
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
pci_cfgfunc_config_device,
{CFG_ETH_IOBASE, CFG_ETH_MEMBASE, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
PCI_FUNC (CFG_ETH_DEV_FN),
pci_cfgfunc_config_device,
{CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
#endif
{ }
{}
};
static struct pci_controller psII_hose = {
config_table: ap1000_config_table,
config_table:ap1000_config_table,
};
void pci_init_board(void)
void pci_init_board (void)
{
struct pci_controller *hose = &psII_hose;
struct pci_controller *hose = &psII_hose;
/*
* Register the hose
*/
hose->first_busno = 0;
hose->last_busno = 0xff;
/*
* Register the hose
*/
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System memory space */
pci_set_region (hose->regions + 0,
AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
AP1000_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* System memory space */
pci_set_region(hose->regions + 0,
AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, AP1000_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI Memory space */
pci_set_region (hose->regions + 1,
PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI Memory space */
pci_set_region(hose->regions + 1,
PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, PSII_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* No IO Memory space - for now */
/* No IO Memory space - for now */
pci_set_ops (hose,
psII_read_config_byte,
psII_read_config_word,
psII_read_config_dword,
psII_write_config_byte,
psII_write_config_word, psII_write_config_dword);
pci_set_ops(hose,
psII_read_config_byte,
psII_read_config_word,
psII_read_config_dword,
psII_write_config_byte,
psII_write_config_word,
psII_write_config_dword);
hose->region_count = 2;
hose->region_count = 2;
pci_register_hose (hose);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = pci_hose_scan (hose);
}

992
board/amirix/ap1000/powerspan.c
View file

File diff suppressed because it is too large Load diff

101
board/amirix/ap1000/serial.c
View file

@ -31,65 +31,59 @@
#include "serial.h"
#endif
const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
const NS16550_t COM_PORTS[] =
{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
#undef CFG_DUART_CHAN
#define CFG_DUART_CHAN gComPort
static int gComPort = 0;
int
serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
(void)NS16550_init(COM_PORTS[0], clock_divisor);
gComPort = 0;
return 0;
}
void
serial_putc(const char c)
{
if (c == '\n'){
NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
}
NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
}
int
serial_getc(void)
{
return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
}
int
serial_tstc(void)
{
return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
}
void
serial_setbrg (void)
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
(void) NS16550_init (COM_PORTS[0], clock_divisor);
gComPort = 0;
return 0;
}
void serial_putc (const char c)
{
if (c == '\n') {
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
}
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
}
int serial_getc (void)
{
return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
}
int serial_tstc (void)
{
return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
NS16550_reinit(COM_PORTS[0], clock_divisor);
NS16550_reinit (COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
NS16550_reinit(COM_PORTS[1], clock_divisor);
NS16550_reinit (COM_PORTS[1], clock_divisor);
#endif
}
void
serial_puts (const char *s)
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
@ -97,32 +91,27 @@ serial_puts (const char *s)
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
void
kgdb_serial_init(void)
void kgdb_serial_init (void)
{
}
void
putDebugChar (int c)
void putDebugChar (int c)
{
serial_putc (c);
}
void
putDebugStr (const char *str)
void putDebugStr (const char *str)
{
serial_puts (str);
}
int
getDebugChar (void)
int getDebugChar (void)
{
return serial_getc();
return serial_getc ();
}
void
kgdb_interruptible (int yes)
void kgdb_interruptible (int yes)
{
return;
}
#endif /* CFG_CMD_KGDB */
#endif /* CFG_CMD_KGDB */

14
cpu/arm720t/serial_netarm.c
View file

@ -35,7 +35,11 @@
#include <asm/hardware.h>
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
#if !defined(CONFIG_NETARM_NS7520)
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
#else
#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
#endif
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
@ -48,8 +52,13 @@
}
#ifndef CONFIG_UART1_CONSOLE
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
#else
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0);
#endif
extern void _netarm_led_FAIL1(void);
@ -62,8 +71,13 @@ void serial_setbrg (void)
DECLARE_GLOBAL_DATA_PTR;
/* set 0 ... make sure pins are configured for serial */
#if !defined(CONFIG_NETARM_NS7520)
PORTA = PORTB =
NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#else
PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#endif
/* first turn em off */
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;

3
cpu/arm720t/start.S
View file

@ -272,12 +272,15 @@ cpu_init_crit:
str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
#ifndef CONFIG_NETARM_PLL_BYPASS
ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
NETARM_GEN_PLL_CTL_POLTST_DEF | \
NETARM_GEN_PLL_CTL_INDIV(1) | \
NETARM_GEN_PLL_CTL_ICP_DEF | \
NETARM_GEN_PLL_CTL_OUTDIV(2) )
str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
#endif
/*
* mask all IRQs by clearing all bits in the INTMRs
*/

2
drivers/Makefile
View file

@ -34,7 +34,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
i8042.o i82365.o inca-ip_sw.o keyboard.o \
lan91c96.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \
ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
ps2ser.o ps2mult.o pc_keyb.o \

849
drivers/ns7520_eth.c Normal file
View file

@ -0,0 +1,849 @@
/***********************************************************************
*
* Copyright (C) 2005 by Videon Central, Inc.
*
* $Id$
* @Author: Arthur Shipkowski
* @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like
* the older netarmeth driver. Note that attempting to filter
* broadcast and multicast out in the SAFR register will cause
* bad things due to released errata.
* @References: [1] NS7520 Hardware Reference, December 2003
* [2] Intel LXT971 Datasheet #249414 Rev. 02
*
***********************************************************************/
#include <common.h>
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
#include <net.h> /* NetSendPacket */
#include <asm/arch/netarm_registers.h>
#include <asm/arch/netarm_dma_module.h>
#include "ns7520_eth.h" /* for Ethernet and PHY */
/**
* Send an error message to the terminal.
*/
#define ERROR(x) \
do { \
char *__foo = strrchr(__FILE__, '/'); \
\
printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
__LINE__, __FUNCTION__); \
printf x; printf("\n"); \
} while (0);
/* some definition to make transistion to linux easier */
#define NS7520_DRIVER_NAME "eth"
#define KERN_WARNING "Warning:"
#define KERN_ERR "Error:"
#define KERN_INFO "Info:"
#if 1
# define DEBUG
#endif
#ifdef DEBUG
# define printk printf
# define DEBUG_INIT 0x0001
# define DEBUG_MINOR 0x0002
# define DEBUG_RX 0x0004
# define DEBUG_TX 0x0008
# define DEBUG_INT 0x0010
# define DEBUG_POLL 0x0020
# define DEBUG_LINK 0x0040
# define DEBUG_MII 0x0100
# define DEBUG_MII_LOW 0x0200
# define DEBUG_MEM 0x0400
# define DEBUG_ERROR 0x4000
# define DEBUG_ERROR_CRIT 0x8000
static int nDebugLvl = DEBUG_ERROR_CRIT;
# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
# define ASSERT( expr, func ) if( !( expr ) ) { \
printf( "Assertion failed! %s:line %d %s\n", \
(int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
func }
#else /* DEBUG */
# define printk(...)
# define DEBUG_ARGS0( FLG, a0 )
# define DEBUG_ARGS1( FLG, a0, a1 )
# define DEBUG_ARGS2( FLG, a0, a1, a2 )
# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
# define DEBUG_FN( n )
# define ASSERT(expr, func)
#endif /* DEBUG */
#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */
#define TX_TIMEOUT (5*CFG_HZ) /* in s */
#define RX_STALL_WORKAROUND_CNT 100
static int ns7520_eth_reset(void);
static void ns7520_link_auto_negotiate(void);
static void ns7520_link_update_egcr(void);
static void ns7520_link_print_changed(void);
/* the PHY stuff */
static char ns7520_mii_identify_phy(void);
static unsigned short ns7520_mii_read(unsigned short uiRegister);
static void ns7520_mii_write(unsigned short uiRegister,
unsigned short uiData);
static unsigned int ns7520_mii_get_clock_divisor(unsigned int
unMaxMDIOClk);
static unsigned int ns7520_mii_poll_busy(void);
static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
static unsigned int uiLastLinkStatus;
static PhyType phyDetected = PHY_NONE;
/***********************************************************************
* @Function: eth_init
* @Return: -1 on failure otherwise 0
* @Descr: Initializes the ethernet engine and uses either FS Forth's default
* MAC addr or the one in environment
***********************************************************************/
int eth_init(bd_t * pbis)
{
unsigned char aucMACAddr[6];
char *pcTmp = getenv("ethaddr");
char *pcEnd;
int i;
DEBUG_FN(DEBUG_INIT);
/* no need to check for hardware */
if (!ns7520_eth_reset())
return -1;
if (NULL == pcTmp)
return -1;
for (i = 0; i < 6; i++) {
aucMACAddr[i] =
pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0;
pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
}
/* configure ethernet address */
*get_eth_reg_addr(NS7520_ETH_SA1) =
aucMACAddr[5] << 8 | aucMACAddr[4];
*get_eth_reg_addr(NS7520_ETH_SA2) =
aucMACAddr[3] << 8 | aucMACAddr[2];
*get_eth_reg_addr(NS7520_ETH_SA3) =
aucMACAddr[1] << 8 | aucMACAddr[0];
/* enable hardware */
*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
*get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
/* the linux kernel may give packets < 60 bytes, for example arp */
*get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
/* Broadcast/multicast allowed; if you don't set this even unicast chokes */
/* Based on NS7520 errata documentation */
*get_eth_reg_addr(NS7520_ETH_SAFR) =
NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
/* enable receive and transmit FIFO, use 10/100 Mbps MII */
*get_eth_reg_addr(NS7520_ETH_EGCR) |=
NS7520_ETH_EGCR_ETXWM_75 |
NS7520_ETH_EGCR_ERX |
NS7520_ETH_EGCR_ERXREG |
NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX;
return 0;
}
/***********************************************************************
* @Function: eth_send
* @Return: -1 on timeout otherwise 1
* @Descr: sends one frame by DMA
***********************************************************************/
int eth_send(volatile void *pPacket, int nLen)
{
int i, length32, retval = 1;
char *pa;
unsigned int *pa32, lastp = 0, rest;
unsigned int status;
pa = (char *) pPacket;
pa32 = (unsigned int *) pPacket;
length32 = nLen / 4;
rest = nLen % 4;
/* make sure there's no garbage in the last word */
switch (rest) {
case 0:
lastp = pa32[length32 - 1];
length32--;
break;
case 1:
lastp = pa32[length32] & 0x000000ff;
break;
case 2:
lastp = pa32[length32] & 0x0000ffff;
break;
case 3:
lastp = pa32[length32] & 0x00ffffff;
break;
}
while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_TXREGE)
== 0) {
}
/* write to the fifo */
for (i = 0; i < length32; i++)
*get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
/* the last word is written to an extra register, this
starts the transmission */
*get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
/* Wait for it to be done */
while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
== 0) {
}
status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */
if (status & NS7520_ETH_ETSR_TXOK) {
retval = 0; /* We're OK! */
} else if (status & NS7520_ETH_ETSR_TXDEF) {
printf("Deferred, we'll see.\n");
retval = 0;
} else if (status & NS7520_ETH_ETSR_TXAL) {
printf("Late collision error, %d collisions.\n",
(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
NS7520_ETH_ETSR_TXCOLC);
} else if (status & NS7520_ETH_ETSR_TXAEC) {
printf("Excessive collisions: %d\n",
(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
NS7520_ETH_ETSR_TXCOLC);
} else if (status & NS7520_ETH_ETSR_TXAED) {
printf("Excessive deferral on xmit.\n");
} else if (status & NS7520_ETH_ETSR_TXAUR) {
printf("Packet underrun.\n");
} else if (status & NS7520_ETH_ETSR_TXAJ) {
printf("Jumbo packet error.\n");
} else {
printf("Error: Should never get here.\n");
}
return (retval);
}
/***********************************************************************
* @Function: eth_rx
* @Return: size of last frame in bytes or 0 if no frame available
* @Descr: gives one frame to U-Boot which has been copied by DMA engine already
* to NetRxPackets[ 0 ].
***********************************************************************/
int eth_rx(void)
{
int i;
unsigned short rxlen;
unsigned short totrxlen = 0;
unsigned int *addr;
unsigned int rxstatus, lastrxlen;
char *pa;
/* If RXBR is 1, data block was received */
while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
/* get status register and the length of received block */
rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
/* clear RXBR to make fifo available */
*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
if (rxstatus & NS7520_ETH_ERSR_ROVER) {
printf("Receive overrun, resetting FIFO.\n");
*get_eth_reg_addr(NS7520_ETH_EGCR) &=
~NS7520_ETH_EGCR_ERX;
udelay(20);
*get_eth_reg_addr(NS7520_ETH_EGCR) |=
NS7520_ETH_EGCR_ERX;
}
if (rxlen == 0) {
printf("Nothing.\n");
return 0;
}
addr = (unsigned int *) NetRxPackets[0];
pa = (char *) NetRxPackets[0];
/* read the fifo */
for (i = 0; i < rxlen / 4; i++) {
*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
addr++;
}
if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXREGR) {
/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
lastrxlen =
((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXFDB_MA) >> 28;
*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
switch (lastrxlen) {
case 1:
*addr &= 0xff000000;
break;
case 2:
*addr &= 0xffff0000;
break;
case 3:
*addr &= 0xffffff00;
break;
}
}
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[0], rxlen - 4);
totrxlen += rxlen - 4;
}
return totrxlen;
}
/***********************************************************************
* @Function: eth_halt
* @Return: n/a
* @Descr: stops the ethernet engine
***********************************************************************/
void eth_halt(void)
{
DEBUG_FN(DEBUG_INIT);
*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
NS7520_ETH_EGCR_ERXDMA |
NS7520_ETH_EGCR_ERXREG |
NS7520_ETH_EGCR_ERXBR |
NS7520_ETH_EGCR_ETX |
NS7520_ETH_EGCR_ETXDMA);
}
/***********************************************************************
* @Function: ns7520_eth_reset
* @Return: 0 on failure otherwise 1
* @Descr: resets the ethernet interface and the PHY,
* performs auto negotiation or fixed modes
***********************************************************************/
static int ns7520_eth_reset(void)
{
DEBUG_FN(DEBUG_MINOR);
/* Reset important registers */
*get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */
*get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
*get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
/* Reset MAC */
*get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
udelay(5);
*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
/* reset and initialize PHY */
*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
/* we don't support hot plugging of PHY, therefore we don't reset
phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
incorrect the first open
may detect the PHY correctly but succeding will fail
For reseting the PHY and identifying we have to use the standard
MDIO CLOCK value 2.5 MHz only after hardware reset
After having identified the PHY we will do faster */
*get_eth_reg_addr(NS7520_ETH_MCFG) =
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* reset PHY */
ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
ns7520_mii_write(PHY_COMMON_CTRL, 0);
udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
/* MII clock has been setup to default, ns7520_mii_identify_phy should
work for all */
if (!ns7520_mii_identify_phy()) {
printk(KERN_ERR NS7520_DRIVER_NAME
": Unsupported PHY, aborting\n");
return 0;
}
/* now take the highest MDIO clock possible after detection */
*get_eth_reg_addr(NS7520_ETH_MCFG) =
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* PHY has been detected, so there can be no abort reason and we can
finish initializing ethernet */
uiLastLinkStatus = 0xff; /* undefined */
ns7520_link_auto_negotiate();
if (phyDetected == PHY_LXT971A)
/* set LED2 to link mode */
ns7520_mii_write(PHY_LXT971_LED_CFG,
(PHY_LXT971_LED_CFG_LINK_ACT <<
PHY_LXT971_LED_CFG_SHIFT_LED2) |
(PHY_LXT971_LED_CFG_TRANSMIT <<
PHY_LXT971_LED_CFG_SHIFT_LED1));
return 1;
}
/***********************************************************************
* @Function: ns7520_link_auto_negotiate
* @Return: void
* @Descr: performs auto-negotation of link.
***********************************************************************/
static void ns7520_link_auto_negotiate(void)
{
unsigned long ulStartJiffies;
unsigned short uiStatus;
DEBUG_FN(DEBUG_LINK);
/* run auto-negotation */
/* define what we are capable of */
ns7520_mii_write(PHY_COMMON_AUTO_ADV,
PHY_COMMON_AUTO_ADV_100BTXFD |
PHY_COMMON_AUTO_ADV_100BTX |
PHY_COMMON_AUTO_ADV_10BTFD |
PHY_COMMON_AUTO_ADV_10BT |
PHY_COMMON_AUTO_ADV_802_3);
/* start auto-negotiation */
ns7520_mii_write(PHY_COMMON_CTRL,
PHY_COMMON_CTRL_AUTO_NEG |
PHY_COMMON_CTRL_RES_AUTO);
/* wait for completion */
ulStartJiffies = get_timer(0);
while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
if ((uiStatus &
(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT))
==
(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
/* lucky we are, auto-negotiation succeeded */
ns7520_link_print_changed();
ns7520_link_update_egcr();
return;
}
}
DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n");
/* ignore invalid link settings */
}
/***********************************************************************
* @Function: ns7520_link_update_egcr
* @Return: void
* @Descr: updates the EGCR and MAC2 link status after mode change or
* auto-negotation
***********************************************************************/
static void ns7520_link_update_egcr(void)
{
unsigned int unEGCR;
unsigned int unMAC2;
unsigned int unIPGT;
DEBUG_FN(DEBUG_LINK);
unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
unIPGT =
*get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
unEGCR &= ~NS7520_ETH_EGCR_EFULLD;
unMAC2 &= ~NS7520_ETH_MAC2_FULLD;
if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
== PHY_LXT971_STAT2_DUPLEX_MODE) {
unEGCR |= NS7520_ETH_EGCR_EFULLD;
unMAC2 |= NS7520_ETH_MAC2_FULLD;
unIPGT |= 0x15; /* see [1] p. 167 */
} else
unIPGT |= 0x12; /* see [1] p. 167 */
*get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
*get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
*get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
}
/***********************************************************************
* @Function: ns7520_link_print_changed
* @Return: void
* @Descr: checks whether the link status has changed and if so prints
* the new mode
***********************************************************************/
static void ns7520_link_print_changed(void)
{
unsigned short uiStatus;
unsigned short uiControl;
DEBUG_FN(DEBUG_LINK);
uiControl = ns7520_mii_read(PHY_COMMON_CTRL);
if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
PHY_COMMON_CTRL_AUTO_NEG) {
/* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
printk(KERN_WARNING NS7520_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
} else {
/* @TODO Linux: carrier_on */
if (phyDetected == PHY_LXT971A) {
uiStatus =
ns7520_mii_read(PHY_LXT971_STAT2);
uiStatus &=
(PHY_LXT971_STAT2_100BTX |
PHY_LXT971_STAT2_DUPLEX_MODE |
PHY_LXT971_STAT2_AUTO_NEG);
/* mask out all uninteresting parts */
}
/* other PHYs must store there link information in
uiStatus as PHY_LXT971 */
}
} else {
/* mode has been forced, so uiStatus should be the same as the
last link status, enforce printing */
uiStatus = uiLastLinkStatus;
uiLastLinkStatus = 0xff;
}
if (uiStatus != uiLastLinkStatus) {
/* save current link status */
uiLastLinkStatus = uiStatus;
/* print new link status */
printk(KERN_INFO NS7520_DRIVER_NAME
": link mode %i Mbps %s duplex %s\n",
(uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
(uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
"half",
(uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
"");
}
}
/***********************************************************************
* the MII low level stuff
***********************************************************************/
/***********************************************************************
* @Function: ns7520_mii_identify_phy
* @Return: 1 if supported PHY has been detected otherwise 0
* @Descr: checks for supported PHY and prints the IDs.
***********************************************************************/
static char ns7520_mii_identify_phy(void)
{
unsigned short uiID1;
unsigned short uiID2;
unsigned char *szName;
char cRes = 0;
DEBUG_FN(DEBUG_MII);
phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
uiID2 = ns7520_mii_read(PHY_COMMON_ID2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
case PHY_NONE:
default:
/* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
address or reset sets the wrong NS7520_ETH_MCFG_CLKS */
uiID2 = 0;
szName = "unknown";
nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
phyDetected = PHY_NONE;
}
printk(KERN_INFO NS7520_DRIVER_NAME
": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
return cRes;
}
/***********************************************************************
* @Function: ns7520_mii_read
* @Return: the data read from PHY register uiRegister
* @Descr: the data read may be invalid if timed out. If so, a message
* is printed but the invalid data is returned.
* The fixed device address is being used.
***********************************************************************/
static unsigned short ns7520_mii_read(unsigned short uiRegister)
{
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be read */
*get_eth_reg_addr(NS7520_ETH_MADR) =
CONFIG_PHY_ADDR << 8 | uiRegister;
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
if (!ns7520_mii_poll_busy())
printk(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in read\n");
/* continue to read */
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
}
/***********************************************************************
* @Function: ns7520_mii_write
* @Return: nothing
* @Descr: writes the data to the PHY register. In case of a timeout,
* no special handling is performed but a message printed
* The fixed device address is being used.
***********************************************************************/
static void ns7520_mii_write(unsigned short uiRegister,
unsigned short uiData)
{
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be written */
*get_eth_reg_addr(NS7520_ETH_MADR) =
CONFIG_PHY_ADDR << 8 | uiRegister;
*get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
if (!ns7520_mii_poll_busy()) {
printf(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in write\n");
}
}
/***********************************************************************
* @Function: ns7520_mii_get_clock_divisor
* @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS
* @Descr: if no clock divisor can be calculated for the
* current SYSCLK and the maximum MDIO Clock, a warning is printed
* and the greatest divisor is taken
***********************************************************************/
static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk)
{
struct {
unsigned int unSysClkDivisor;
unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */
} PHYClockDivisors[] = {
{
4, NS7520_ETH_MCFG_CLKS_4}, {
6, NS7520_ETH_MCFG_CLKS_6}, {
8, NS7520_ETH_MCFG_CLKS_8}, {
10, NS7520_ETH_MCFG_CLKS_10}, {
14, NS7520_ETH_MCFG_CLKS_14}, {
20, NS7520_ETH_MCFG_CLKS_20}, {
28, NS7520_ETH_MCFG_CLKS_28}
};
int nIndexSysClkDiv;
int nArraySize =
sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]);
unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to
greatest div */
DEBUG_FN(DEBUG_INIT);
for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
nIndexSysClkDiv++) {
/* find first sysclock divisor that isn't higher than 2.5 MHz
clock */
if (NETARM_XTAL_FREQ /
PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
unMaxMDIOClk) {
unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
break;
}
}
DEBUG_ARGS2(DEBUG_INIT,
"Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
unClks, unMaxMDIOClk);
/* return greatest divisor */
return unClks;
}
/***********************************************************************
* @Function: ns7520_mii_poll_busy
* @Return: 0 if timed out otherwise the remaing timeout
* @Descr: waits until the MII has completed a command or it times out
* code may be interrupted by hard interrupts.
* It is not checked what happens on multiple actions when
* the first is still being busy and we timeout.
***********************************************************************/
static unsigned int ns7520_mii_poll_busy(void)
{
unsigned int unTimeout = 1000;
DEBUG_FN(DEBUG_MII_LOW);
while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
== NS7520_ETH_MIND_BUSY) && unTimeout)
unTimeout--;
return unTimeout;
}
/* ----------------------------------------------------------------------------
* Net+ARM ethernet MII functionality.
*/
#if defined(CONFIG_MII)
/**
* Maximum MII address we support
*/
#define MII_ADDRESS_MAX (31)
/**
* Maximum MII register address we support
*/
#define MII_REGISTER_MAX (31)
/**
* Ethernet MII interface return values for public functions.
*/
enum mii_status {
MII_STATUS_SUCCESS = 0,
MII_STATUS_FAILURE = 1,
};
/**
* Read a 16-bit value from an MII register.
*/
extern int miiphy_read(unsigned char const addr, unsigned char const reg,
unsigned short *const value)
{
int ret = MII_STATUS_FAILURE;
/* Parameter checks */
if (addr > MII_ADDRESS_MAX) {
ERROR(("invalid addr, 0x%02X", addr));
goto miiphy_read_failed_0;
}
if (reg > MII_REGISTER_MAX) {
ERROR(("invalid reg, 0x%02X", reg));
goto miiphy_read_failed_0;
}
if (value == NULL) {
ERROR(("NULL value"));
goto miiphy_read_failed_0;
}
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be read */
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
if (!ns7520_mii_poll_busy())
printk(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in read\n");
/* continue to read */
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
*value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
ret = MII_STATUS_SUCCESS;
/* Fall through */
miiphy_read_failed_0:
return (ret);
}
/**
* Write a 16-bit value to an MII register.
*/
extern int miiphy_write(unsigned char const addr, unsigned char const reg,
unsigned short const value)
{
int ret = MII_STATUS_FAILURE;
/* Parameter checks */
if (addr > MII_ADDRESS_MAX) {
ERROR(("invalid addr, 0x%02X", addr));
goto miiphy_write_failed_0;
}
if (reg > MII_REGISTER_MAX) {
ERROR(("invalid reg, 0x%02X", reg));
goto miiphy_write_failed_0;
}
/* write MII register to be written */
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
*get_eth_reg_addr(NS7520_ETH_MWTD) = value;
if (!ns7520_mii_poll_busy()) {
printf(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in write\n");
}
ret = MII_STATUS_SUCCESS;
/* Fall through */
miiphy_write_failed_0:
return (ret);
}
#endif /* defined(CONFIG_MII) */
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */

22
include/asm-arm/arch-arm720t/netarm_gen_module.h
View file

@ -1,6 +1,9 @@
/*
* include/asm-armnommu/arch-netarm/netarm_gen_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_GEN_MODULE_REGISTERS_H
@ -49,7 +54,9 @@
#define NETARM_GEN_TIMER2_STATUS (0x1c)
#define NETARM_GEN_PORTA (0x20)
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORTB (0x24)
#endif
#define NETARM_GEN_PORTC (0x28)
#define NETARM_GEN_INTR_ENABLE (0x30)
@ -128,8 +135,14 @@
/* PORT C Register ( 0xFFB0_0028 ) */
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
#else
#define NETARM_GEN_PORT_MODE(x) ((x)<<24)
#define NETARM_GEN_PORT_DIR(x) ((x)<<16)
#define NETARM_GEN_PORT_CSF(x) ((x)<<8)
#endif
/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
@ -143,10 +156,15 @@
#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
#if ~defined(CONFIG_NETARM_NS7520)
#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
#else
#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF)
#endif
/* prescale to msecs conversion */
#if !defined(CONFIG_NETARM_PLL_BYPASS)
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
@ -155,9 +173,7 @@
NETARM_GEN_TSTAT_CTC_MASK ) | \
NETARM_GEN_TCTL_USE_PRESCALE )
#if 0
/* ifdef CONFIG_NETARM_PLL_BYPASS else */
#error test
#else
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )

27
include/asm-arm/arch-arm720t/netarm_mem_module.h
View file

@ -1,6 +1,9 @@
/*
* include/asm-armnommu/arch-netarm/netarm_mem_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_MEM_MODULE_REGISTERS_H
@ -154,4 +159,26 @@
#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
#ifdef CONFIG_NETARM_NS7520
/* The NS7520 has a second options register for each chip select */
#define NETARM_MEM_CS0_OPTIONS_B (0x18)
#define NETARM_MEM_CS1_OPTIONS_B (0x28)
#define NETARM_MEM_CS2_OPTIONS_B (0x38)
#define NETARM_MEM_CS3_OPTIONS_B (0x48)
#define NETARM_MEM_CS4_OPTIONS_B (0x58)
/* Option B Registers (0xFFC0_00x8) */
#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001)
#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002)
#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
#endif
#endif

19
include/asm-arm/arch-arm720t/netarm_registers.h
View file

@ -1,6 +1,9 @@
/*
* linux/include/asm-arm/arch-netarm/netarm_registers.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 WireSpeed Communications Corporation
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NET_ARM_REGISTERS_H
@ -38,6 +43,8 @@
/* the input crystal/clock frequency ( in Hz ) */
#define NETARM_XTAL_FREQ_25MHz (18432000)
#define NETARM_XTAL_FREQ_33MHz (23698000)
#define NETARM_XTAL_FREQ_48MHz (48000000)
#define NETARM_XTAL_FREQ_55MHz (55000000)
#define NETARM_XTAL_FREQ_EMLIN1 (20000000)
/* the frequency of SYS_CLK */
@ -60,12 +67,22 @@
#define NETARM_PLL_COUNT_VAL 4
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#else /* CONFIG_NETARM_NET50 */
#elif defined(CONFIG_NETARM_NET50)
/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
#define NETARM_PLL_COUNT_VAL 8
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#else /* CONFIG_NETARM_NS7520 */
#define NETARM_PLL_COUNT_VAL 0
#if defined(CONFIG_BOARD_UNC20)
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz
#else
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz
#endif
#endif
/* #include "arm_registers.h" */

149
include/configs/AP1000.h
View file

@ -24,14 +24,14 @@
#undef DEBUG
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_AP1000 1 /* ...on an AP1000 board */
#define CONFIG_PCI 1
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT "0> "
#define CFG_PROMPT_HUSH_PS2 "> "
@ -39,7 +39,7 @@
#define CONFIG_COMMAND_HISTORY 1
#define CONFIG_COMPLETE_ADDRESSES 1
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_USE_BUFFER_WRITE
#ifdef CFG_ENV_IS_IN_NVRAM
@ -50,39 +50,37 @@
#endif
#endif
#define CONFIG_BAUDRATE 57600
#define CONFIG_BAUDRATE 57600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_BOOTCOMMAND "" /* autoboot command */
#define CONFIG_BOOTCOMMAND "" /* autoboot command */
/* Size (bytes) of interrupt driven serial port buffer.
* Set to 0 to use polling instead of interrupts.
* Setting to 0 will also disable RTS/CTS handshaking.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_BOOTARGS "console=ttyS0,57600"
#define CONFIG_BOOTARGS "console=ttyS0,57600"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & \
(~CFG_CMD_RTC) & ~(CFG_CMD_I2C)) | \
CFG_CMD_IRQ | \
CFG_CMD_PCI | \
CFG_CMD_DHCP | \
CFG_CMD_ASKENV | \
CFG_CMD_ELF | \
CFG_CMD_PING | \
CFG_CMD_MVENV \
)
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & \
(~CFG_CMD_RTC) & ~(CFG_CMD_I2C)) | \
CFG_CMD_IRQ | \
CFG_CMD_PCI | \
CFG_CMD_DHCP | \
CFG_CMD_ASKENV | \
CFG_CMD_ELF | \
CFG_CMD_PING | \
CFG_CMD_MVENV \
)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SYS_CLK_FREQ 30000000
@ -91,20 +89,20 @@
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_ALT_MEMTEST 1
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
#define CFG_ALT_MEMTEST 1
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
@ -115,86 +113,84 @@
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_NS16550_CLK 40000000
#define CFG_DUART_CHAN 0
#define CFG_NS16550_CLK 40000000
#define CFG_DUART_CHAN 0
#define CFG_NS16550_COM1 (0x4C000000 + 0x1000)
#define CFG_NS16550_COM2 (0x4C800000 + 0x1000)
#define CFG_NS16550_REG_SIZE 4
#define CFG_NS16550 1
#define CFG_INIT_CHAN1 1
#define CFG_INIT_CHAN2 0
#define CFG_INIT_CHAN1 1
#define CFG_INIT_CHAN2 0
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x20000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x20000000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI 1
#define CFG_PROGFLASH_BASE CFG_FLASH_BASE
#define CFG_CONFFLASH_BASE 0x24000000
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
/* BEG ENVIRONNEMENT FLASH */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */
#endif
/* END ENVIRONNEMENT FLASH */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
@ -203,9 +199,8 @@
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
@ -214,29 +209,29 @@
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
#define SPD_EEPROM_ADDRESS 0x50
#define SPD_EEPROM_ADDRESS 0x50
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* JFFS2 stuff */
@ -248,8 +243,8 @@
#define CONFIG_NET_MULTI
#define CONFIG_E1000
#define CFG_ETH_DEV_FN 0x0800
#define CFG_ETH_IOBASE 0x31000000
#define CFG_ETH_MEMBASE 0x32000000
#define CFG_ETH_DEV_FN 0x0800
#define CFG_ETH_IOBASE 0x31000000
#define CFG_ETH_MEMBASE 0x32000000
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */

335
include/ns7520_eth.h Normal file
View file

@ -0,0 +1,335 @@
/***********************************************************************
*
* Copyright 2003 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id$
* @Author: Markus Pietrek
* @Descr: Defines the NS7520 ethernet registers.
* Stick with the old ETH prefix names instead going to the
* new EFE names in the manual.
* NS7520_ETH_* refer to NS7520 Hardware
* Reference/January 2003 [1]
* PHY_LXT971_* refer to Intel LXT971 Datasheet
* #249414 Rev. 02 [2]
* Partly derived from netarm_eth_module.h
*
* Modified by Arthur Shipkowski <art@videon-central.com> from the
* Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
*
***********************************************************************/
#ifndef FS_NS7520_ETH_H
#define FS_NS7520_ETH_H
#ifdef CONFIG_DRIVER_NS7520_ETHERNET
#include "lxt971a.h"
/* The port addresses */
#define NS7520_ETH_MODULE_BASE (0xFF800000)
#define get_eth_reg_addr(c) \
((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
#define NS7520_ETH_TEST (0x041C) /* Test Register */
#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
/* EGCR Ethernet General Control Register Bit Fields*/
#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
/* EGSR Ethernet General Status Register Bit Fields*/
#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
/* ETSR Ethernet Transmit Status Register Bit Fields*/
#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
/* ERSR Ethernet Receive Status Register Bit Fields*/
#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
/* MAC1 MAC Configuration Register 1 Bit Fields*/
#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
/* MAC Configuration Register 2 Bit Fields*/
#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
/* MAXF Maximum Frame Register Bit Fields*/
#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
/* SUPP PHY Support Register Bit Fields*/
#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
/* TEST Register Bit Fields*/
#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
/* MCFG MII Management Configuration Register Bit Fields*/
#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
/* MCMD MII Management Command Register Bit Fields*/
#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
/* MCMD MII Management Address Register Bit Fields*/
#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
/* MWTD MII Management Write Data Register Bit Fields*/
#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
/* MRRD MII Management Read Data Register Bit Fields*/
#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
/* MIND MII Management Indicators Register Bit Fields*/
#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
/* SMII Status Register Bit Fields*/
#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
/* SA1 Station Address 1 Register Bit Fields*/
#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
/* SA2 Station Address 2 Register Bit Fields*/
#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
/* SA3 Station Address 3 Register Bit Fields*/
#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
/* SAFR Station Address Filter Register Bit Fields*/
#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
/* HT1 Hash Table 1 Register Bit Fields*/
#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
/* HT2 Hash Table 2 Register Bit Fields*/
#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
/* HT3 Hash Table 3 Register Bit Fields*/
#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
/* HT4 Hash Table 4 Register Bit Fields*/
#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
#endif /* FS_NS7520_ETH_H */