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c624d07f3f
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _RESET_MANAGER_H_
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#define _RESET_MANAGER_H_
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void reset_cpu(ulong addr);
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void reset_deassert_peripherals_handoff(void);
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void socfpga_bridges_reset(int enable);
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void socfpga_per_reset(u32 reset, int set);
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void socfpga_per_reset_all(void);
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struct socfpga_reset_manager {
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u32 status;
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u32 ctrl;
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u32 counts;
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u32 padding1;
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u32 mpu_mod_reset;
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u32 per_mod_reset;
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u32 per2_mod_reset;
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u32 brg_mod_reset;
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u32 misc_mod_reset;
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u32 tstscratch;
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};
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
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#else
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
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#endif
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/*
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* Define a reset identifier, from which a permodrst bank ID
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* and reset ID can be extracted using the subsequent macros
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* RSTMGR_RESET() and RSTMGR_BANK().
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*/
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#define RSTMGR_BANK_OFFSET 8
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#define RSTMGR_BANK_MASK 0x7
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#define RSTMGR_RESET_OFFSET 0
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#define RSTMGR_RESET_MASK 0x1f
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#define RSTMGR_DEFINE(_bank, _offset) \
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((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
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/* Extract reset ID from the reset identifier. */
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#define RSTMGR_RESET(_reset) \
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(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
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/* Extract bank ID from the reset identifier. */
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#define RSTMGR_BANK(_reset) \
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(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
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/*
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* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... permodrst
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* 2 ... per2modrst
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* 3 ... brgmodrst
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* 4 ... miscmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
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#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
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#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
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#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
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/* Create a human-readable reference to SoCFPGA reset. */
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#define SOCFPGA_RESET(_name) RSTMGR_##_name
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#endif /* _RESET_MANAGER_H_ */
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