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https://github.com/AsahiLinux/u-boot
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21385adf2c
BCM63138 is an ARM A9 based DSL Broadband SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory, ARM A9 global timer and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are stripped down version of linux copies with mininum blocks needed by u-boot. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. This patch applies on top of the my previous patch [1]. [1] https://lists.denx.de/pipermail/u-boot/2022-August/490570.html Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
149 lines
3.1 KiB
Text
149 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Broadcom BCM63138 DSL SoCs Device Tree
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,bcm63138", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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enable-method = "brcm,bcm63138";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <1>;
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enable-method = "brcm,bcm63138";
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};
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};
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clocks {
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/* UBUS peripheral clock */
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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/* peripheral clock for system timer */
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axi_clk: axi_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/* APB bus clock */
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apb_clk: apb_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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/* ARM bus */
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axi@80000000 {
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compatible = "simple-bus";
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ranges = <0 0x80000000 0x784000>;
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#address-cells = <1>;
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#size-cells = <1>;
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L2: cache-controller@1d000 {
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compatible = "arm,pl310-cache";
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reg = <0x1d000 0x1000>;
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cache-unified;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <1024>;
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cache-line-size = <32>;
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interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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scu: scu@1e000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1e000 0x100>;
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};
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gic: interrupt-controller@1f000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x1f000 0x1000
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0x1e100 0x100>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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};
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global_timer: timer@1e200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1e200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&axi_clk>;
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};
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local_timer: local-timer@1e600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1e600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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clocks = <&axi_clk>;
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};
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twd_watchdog: watchdog@1e620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1e620 0x20>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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armpll: armpll@20000 {
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#clock-cells = <0>;
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compatible = "brcm,bcm63138-armpll";
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clocks = <&periph_clk>;
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reg = <0x20000 0xf00>;
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};
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};
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/* Legacy UBUS base */
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bus@fffe8000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffe8000 0x8000>;
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timer0: timer@80 {
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compatible = "brcm,bcmbca-periph-timer";
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reg = <0x80 0x28>;
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clocks = <&periph_clk>;
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};
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uart0: serial@600 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x600 0x20>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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