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https://github.com/AsahiLinux/u-boot
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4a3efd71cd
In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as a continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.
However there is an 'ALIGN(8)' between these 2 sections which might
cause a gap to be inserted between these 2 sections to satisfy the
alignment requirement on RV32. This would break the assumption of
the prelink process and generate an unbootable image.
Fixes: 9a6569a043 ("riscv: Update alignment for some sections in linker scripts")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
85 lines
1.2 KiB
Text
85 lines
1.2 KiB
Text
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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OUTPUT_ARCH("riscv")
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ENTRY(_start)
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SECTIONS
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{
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. = ALIGN(4);
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.text : {
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arch/riscv/cpu/start.o (.text)
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}
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/* This needs to come before *(.text*) */
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.efi_runtime : {
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__efi_runtime_start = .;
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*(.text.efi_runtime*)
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*(.rodata.efi_runtime*)
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*(.data.efi_runtime*)
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__efi_runtime_stop = .;
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}
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.text_rest : {
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*(.text*)
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}
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
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. = ALIGN(4);
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.data : {
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*(.data*)
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}
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. = ALIGN(4);
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.got : {
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__got_start = .;
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*(.got.plt) *(.got)
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__got_end = .;
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}
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. = ALIGN(4);
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__u_boot_list : {
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KEEP(*(SORT(__u_boot_list*)));
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}
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. = ALIGN(8);
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.efi_runtime_rel : {
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__efi_runtime_rel_start = .;
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*(.rel*.efi_runtime)
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*(.rel*.efi_runtime.*)
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__efi_runtime_rel_stop = .;
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}
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/DISCARD/ : { *(.rela.plt*) }
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.rela.dyn : {
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__rel_dyn_start = .;
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*(.rela*)
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__rel_dyn_end = .;
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}
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. = ALIGN(8);
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.dynsym : {
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__dyn_sym_start = .;
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*(.dynsym)
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__dyn_sym_end = .;
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}
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. = ALIGN(8);
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_end = .;
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.bss : {
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__bss_start = .;
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*(.bss*)
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. = ALIGN(8);
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__bss_end = .;
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}
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}
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