Bin Meng 9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT ... As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>		2023-07-12 13:21:40 +08:00
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cpu.c	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
dram.c	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
Kconfig	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
Makefile	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
spl.c	ram: starfive: Read memory size information from EEPROM	2023-07-12 13:21:40 +08:00