4 commits

Author	SHA1	Message	Date
Bin Meng	9675d92027	riscv: Rename SiFive CLINT to RISC-V ALINT ... As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>	2023-07-12 13:21:40 +08:00
Yanhong Wang	38d900b409	ram: starfive: Read memory size information from EEPROM ... StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of DDR capacity includes 2G/4G/8G, a DT can not support multiple capacities, so the capacity size information is recorded to EEPROM, when DDR initialization required capacity size information is read from EEPROM. If there is no information in EEPROM, it is initialized with the default size defined in DT. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2023-07-12 13:21:40 +08:00
Yanhong Wang	2f5fad0b0d	riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC ... Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>	2023-04-20 16:08:44 +08:00
Yanhong Wang	218534153e	riscv: cpu: jh7110: Add support for jh7110 SoC ... Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>	2023-04-20 16:08:44 +08:00