mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
a1e384b4d9
This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
44 lines
899 B
C
44 lines
899 B
C
#ifndef DT_BINDINGS_STM32_SDRAM_H
|
|
#define DT_BINDINGS_STM32_SDRAM_H
|
|
|
|
#define NO_COL_8 0x0
|
|
#define NO_COL_9 0x1
|
|
#define NO_COL_10 0x2
|
|
#define NO_COL_11 0x3
|
|
|
|
#define NO_ROW_11 0x0
|
|
#define NO_ROW_12 0x1
|
|
#define NO_ROW_13 0x2
|
|
|
|
#define MWIDTH_8 0x0
|
|
#define MWIDTH_16 0x1
|
|
#define MWIDTH_32 0x2
|
|
#define BANKS_2 0x0
|
|
#define BANKS_4 0x1
|
|
#define CAS_1 0x1
|
|
#define CAS_2 0x2
|
|
#define CAS_3 0x3
|
|
#define SDCLK_DIS 0x0
|
|
#define SDCLK_2 0x2
|
|
#define SDCLK_3 0x3
|
|
#define RD_BURST_EN 0x1
|
|
#define RD_BURST_DIS 0x0
|
|
#define RD_PIPE_DL_0 0x0
|
|
#define RD_PIPE_DL_1 0x1
|
|
#define RD_PIPE_DL_2 0x2
|
|
|
|
/* Timing = value +1 cycles */
|
|
#define TMRD_1 (1 - 1)
|
|
#define TMRD_2 (2 - 1)
|
|
#define TXSR_1 (1 - 1)
|
|
#define TXSR_6 (6 - 1)
|
|
#define TRAS_1 (1 - 1)
|
|
#define TRAS_4 (4 - 1)
|
|
#define TRC_6 (6 - 1)
|
|
#define TWR_1 (1 - 1)
|
|
#define TWR_2 (2 - 1)
|
|
#define TRP_2 (2 - 1)
|
|
#define TRCD_1 (1 - 1)
|
|
#define TRCD_2 (2 - 1)
|
|
|
|
#endif
|