mirror of
https://github.com/AsahiLinux/u-boot
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264 lines
6.9 KiB
C
264 lines
6.9 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <mpc8xx.h>
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#include "pld.h"
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#include "hpi.h"
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#define _NOT_USED_ 0xFFFFFFFF
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static long int dram_size (long int, long int *, long int);
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMB RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMB RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMB RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMB RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMB RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMB RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMB RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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long int initdram (int board_type)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
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long int size_b0;
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long int size8, size9;
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int i;
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/*
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* Configure UPMB for SDRAM
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*/
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upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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udelay(100);
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memctl->memc_mptpr = CFG_MPTPR;
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/* burst length=4, burst type=sequential, CAS latency=2 */
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memctl->memc_mar = CFG_MAR;
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/*
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* Map controller bank 1 to the SDRAM bank at preliminary address.
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*/
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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/* initialize memory address register */
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memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
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/* mode initialization (offset 5) */
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udelay (200); /* 0x80006105 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
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/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
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udelay (1); /* 0x80006130 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
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udelay (1); /* 0x80006130 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
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udelay (1); /* 0x80006106 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
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memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
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udelay (200);
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/* Need at least 10 DRAM accesses to stabilize */
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for (i = 0; i < 10; ++i) {
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volatile unsigned long *addr =
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(volatile unsigned long *) CFG_SDRAM_BASE;
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unsigned long val;
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val = *(addr + i);
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*(addr + i) = val;
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}
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
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udelay (500);
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
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udelay (500);
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}
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/*
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* Final mapping:
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*/
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memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
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OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
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memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
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udelay (1000);
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/* initalize the DSP Host Port Interface */
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hpi_init();
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/* FRAM Setup */
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memctl->memc_or4 = CFG_OR4;
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memctl->memc_br4 = CFG_BR4;
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udelay(1000);
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return (size_b0);
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mbmr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mbmr = mbmr_value;
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return (get_ram_size (base, maxsize));
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}
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/************* other stuff ******************/
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int board_early_init_f(void)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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/* Set Go/NoGo led (PA15) to color red */
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immap->im_ioport.iop_papar &= ~0x1;
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immap->im_ioport.iop_paodr &= ~0x1;
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immap->im_ioport.iop_padir |= 0x1;
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immap->im_ioport.iop_padat |= 0x1;
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#if 0
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/* Turn on LED PD9 */
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immap->im_ioport.iop_pdpar &= ~(0x0040);
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immap->im_ioport.iop_pddir |= 0x0040;
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immap->im_ioport.iop_pddat |= 0x0040;
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#endif
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/*
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* Enable console on SMC1. This requires turning on
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* the com2_en signal and SMC1_DISABLE
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*/
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/* SMC1_DISABLE: PB17 */
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immap->im_cpm.cp_pbodr &= ~0x4000;
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immap->im_cpm.cp_pbpar &= ~0x4000;
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immap->im_cpm.cp_pbdir |= 0x4000;
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immap->im_cpm.cp_pbdat &= ~0x4000;
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/* COM2_EN: PD10 */
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immap->im_ioport.iop_pdpar &= ~0x0020;
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immap->im_ioport.iop_pddir &= ~0x4000;
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immap->im_ioport.iop_pddir |= 0x0020;
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immap->im_ioport.iop_pddat |= 0x0020;
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#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
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immap->im_cpm.cp_simode |= 0x7000;
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immap->im_cpm.cp_simode &= ~(0x8000);
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#endif
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return 0;
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}
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int last_stage_init(void)
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{
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#ifdef CONFIG_SPC1920_HPI_TEST
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printf("CMB1920 Host Port Interface Test: %s\n",
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hpi_test() ? "Failed!" : "OK");
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#endif
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return 0;
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}
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int checkboard (void)
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{
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puts("Board: SPC1920\n");
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return 0;
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}
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