mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
71d2a5e5ef
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
The following script has been used for the synchronization:
$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
else
echo "NOT FOUND: $i"
fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )
Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.
Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.
Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .
Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .
Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
128 lines
2.9 KiB
Text
128 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
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* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "hihope-common.dtsi"
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/ {
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audio_clkout: audio-clkout {
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/*
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* This is same as <&rcar_sound 0>
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* but needed to avoid cs2000/rcar_sound probe dead-lock
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*/
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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};
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wlan_en_reg: regulator-wlan_en {
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compatible = "regulator-fixed";
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regulator-name = "wlan-en-regulator";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <70000>;
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gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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x1801_clk: x1801-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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};
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&hscif0 {
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bluetooth {
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compatible = "ti,wl1837-st";
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enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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};
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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status = "okay";
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cs2000: clk_multiplier@4f {
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#clock-cells = <0>;
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compatible = "cirrus,cs2000-cp";
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reg = <0x4f>;
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clocks = <&audio_clkout>, <&x1801_clk>;
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clock-names = "clk_in", "ref_clk";
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assigned-clocks = <&cs2000>;
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assigned-clock-rates = <24576000>; /* 1/1 divide */
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};
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};
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&pfc {
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i2c2_pins: i2c2 {
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groups = "i2c2_a";
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function = "i2c2";
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};
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sound_clk_pins: sound_clk {
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groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
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function = "audio_clk";
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};
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sound_pins: sound {
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groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
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function = "ssi";
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};
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};
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&rcar_sound {
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pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* Single DAI */
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#sound-dai-cells = <0>;
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/* audio_clkout0/1/2/3 */
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#clock-cells = <1>;
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clock-frequency = <12288000 11289600>;
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/*
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* Update <audio_clk_b> to <cs2000>
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* Switch SW2404 should be at position 1 so that clock from
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* CS2000 is connected to AUDIO_CLKB_A
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*/
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clocks = <&cpg CPG_MOD 1005>,
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<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
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<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
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<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
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<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
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<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
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<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
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<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
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<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
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<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
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<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
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<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
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<&audio_clk_a>, <&cs2000>,
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<&audio_clk_c>,
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<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
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rsnd_port: port {
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rsnd_endpoint: endpoint {
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remote-endpoint = <&dw_hdmi0_snd_in>;
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dai-format = "i2s";
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bitclock-master = <&rsnd_endpoint>;
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frame-master = <&rsnd_endpoint>;
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playback = <&ssi2>;
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};
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};
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};
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