mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
298 lines
6.7 KiB
Text
298 lines
6.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm QCS404 based evaluation board device tree source
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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/ {
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model = "Qualcomm Technologies, Inc. QCS404 EVB";
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compatible = "qcom,qcs404-evb", "qcom,qcs404";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &debug_uart;
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};
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memory {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0x0 0x0 0x0 0xffffffff>;
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compatible = "simple-bus";
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soc_gpios: pinctrl_north@1300000 {
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compatible = "qcom,qcs404-pinctrl";
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reg = <0x1300000 0x200000>;
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gpio-controller;
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gpio-count = <120>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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blsp1_uart2: uart {
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pins = "GPIO_17", "GPIO_18";
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function = "blsp_uart2";
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};
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ethernet_defaults: ethernet-defaults {
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int {
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pins = "GPIO_61";
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function = "rgmii_int";
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bias-disable;
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drive-strength = <2>;
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};
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mdc {
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pins = "GPIO_76";
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function = "rgmii_mdc";
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bias-pull-up;
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};
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mdio {
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pins = "GPIO_75";
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function = "rgmii_mdio";
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bias-pull-up;
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};
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tx {
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pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
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function = "rgmii_tx";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx {
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pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
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function = "rgmii_rx";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ctl {
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pins = "GPIO_68";
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function = "rgmii_ctl";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ctl {
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pins = "GPIO_74";
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function = "rgmii_ctl";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ck {
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pins = "GPIO_63";
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function = "rgmii_ck";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ck {
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pins = "GPIO_69";
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function = "rgmii_ck";
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bias-disable;
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drive-strength = <2>;
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};
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-qcs404";
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reg = <0x1800000 0x80000>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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#clock-cells = <1>;
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};
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reset: gcc-reset@1800000 {
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compatible = "qcom,gcc-reset-qcs404";
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reg = <0x1800000 0x80000>;
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#reset-cells = <1>;
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};
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debug_uart: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4";
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reg = <0x78b1000 0x200>;
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clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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bit-rate = <0xFF>;
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pinctrl-names = "uart";
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pinctrl-0 = <&blsp1_uart2>;
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};
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sdhci@7804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000 0x7805000 0x1000>;
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clock = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>;
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bus-width = <0x8>;
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index = <0x0>;
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non-removable;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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};
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usb3_phy: phy@78000 {
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compatible = "qcom,usb-ss-28nm-phy";
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#phy-cells = <0>;
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reg = <0x78000 0x400>;
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clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&gcc GCC_USB3_PHY_PIPE_CLK>;
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clock-names = "ahb", "pipe";
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resets = <&reset GCC_USB3_PHY_BCR>,
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<&reset GCC_USB3PHY_PHY_BCR>;
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reset-names = "com", "phy";
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};
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usb2_phy_prim: phy@7a000 {
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compatible = "qcom,usb-hs-28nm-femtophy";
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#phy-cells = <0>;
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reg = <0x7a000 0x200>;
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clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ahb", "sleep";
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resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
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<&reset GCC_USB2A_PHY_BCR>;
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reset-names = "phy", "por";
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};
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usb2_phy_sec: phy@7c000 {
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compatible = "qcom,usb-hs-28nm-femtophy";
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#phy-cells = <0>;
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reg = <0x7c000 0x200>;
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clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ahb", "sleep";
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resets = <&reset GCC_QUSB2_PHY_BCR>,
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<&reset GCC_USB2_HS_PHY_ONLY_BCR>;
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reset-names = "phy", "por";
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};
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usb3: usb@7678800 {
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compatible = "qcom,dwc3";
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reg = <0x7678800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>;
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clock-names = "core", "iface", "sleep", "mock_utmi";
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dwc3@7580000 {
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compatible = "snps,dwc3";
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reg = <0x7580000 0xcd00>;
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phys = <&usb2_phy_prim>, <&usb3_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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dr_mode = "host";
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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};
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usb2: usb@79b8800 {
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compatible = "qcom,dwc3";
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reg = <0x79b8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
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<&gcc GCC_PCNOC_USB2_CLK>,
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<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
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<&gcc GCC_USB20_MOCK_UTMI_CLK>;
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clock-names = "core", "iface", "sleep", "mock_utmi";
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dwc3@78c0000 {
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compatible = "snps,dwc3";
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reg = <0x78c0000 0xcc00>;
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phys = <&usb2_phy_sec>;
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phy-names = "usb2-phy";
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dr_mode = "peripheral";
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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maximum-speed = "high-speed";
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};
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};
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ethernet: ethernet@7a80000 {
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compatible = "qcom,qcs404-ethqos";
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reg = <0x07a80000 0x10000>,
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<0x07a96000 0x100>;
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reg-names = "stmmaceth", "rgmii";
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clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
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clocks = <&gcc GCC_ETH_AXI_CLK>,
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<&gcc GCC_ETH_SLAVE_AHB_CLK>,
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<&gcc GCC_ETH_PTP_CLK>,
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<&gcc GCC_ETH_RGMII_CLK>;
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resets = <&reset GCC_EMAC_BCR>;
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reset-names = "emac";
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snps,tso;
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rx-fifo-depth = <4096>;
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tx-fifo-depth = <4096>;
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snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 10000>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_defaults>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii";
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max-speed = <1000>;
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mdio {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "snps,dwmac-mdio";
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phy1: phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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device_type = "ethernet-phy";
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reg = <0x3>;
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};
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};
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};
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spmi@200f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x200f000 0x1000
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0x2400000 0x400000
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0x2c00000 0x400000>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pms405_0: pms405@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0x0 0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pms405_gpios: pms405_gpios@c000 {
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compatible = "qcom,pms405-gpio";
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reg = <0xc000 0x400>;
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gpio-controller;
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gpio-count = <12>;
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#gpio-cells = <2>;
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gpio-bank-name="pmic";
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};
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};
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};
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};
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};
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#include "qcs404-evb-uboot.dtsi"
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