York Sun dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378 ... Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com>		2015-01-23 22:29:13 -06:00
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clock.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
config.h	arm/ls1021a: Add workaround for DDR erratum A008378	2015-01-23 22:29:13 -06:00
fsl_serdes.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
immap_ls102xa.h	ls102xa: changing a few targets' configurations.	2014-12-11 09:42:03 -08:00
imx-regs.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
ls102xa_stream_id.h	ARM: ls102xa: Setting device's stream id for SMMUs.	2014-12-11 09:42:22 -08:00
ns_access.h	ARM: ls102xa: allow all the peripheral access permission as R/W.	2014-12-11 09:42:12 -08:00
spl.h	arm: ls102xa: Add SD boot support for LS1021AQDS board	2014-12-11 09:39:22 -08:00