u-boot/arch/arm/cpu/armv7/omap5
Nishanth Menon 3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
..
clocks.c OMAP4460: TPS Ensure SET1 is selected after voltage configuration 2012-05-15 08:31:22 +02:00
config.mk omap5: Add minimal support for omap5430. 2011-11-15 22:25:50 +01:00
emif.c omap5: emif: Add emif/ddr configurations required for omap5 evm 2011-11-15 22:25:50 +01:00
hwinit.c omap5: Add minimal support for omap5430. 2011-11-15 22:25:50 +01:00
Makefile omap5: Add minimal support for omap5430. 2011-11-15 22:25:50 +01:00
sdram_elpida.c omap5: emif: Add emif/ddr configurations required for omap5 evm 2011-11-15 22:25:50 +01:00