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6 commits

Author SHA1 Message Date
Nishanth Menon
3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
a78274b205 OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Sricharan
78f455c055 omap4/5: Add support for booting with CH.
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.

Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
bb772a5944 omap5: emif: Add emif/ddr configurations required for omap5 evm
Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.

Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
2e5ba48928 omap5: clocks: Add clocks support for omap5 platform.
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.

Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
508a58fa8e omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00