mirror of
https://github.com/AsahiLinux/u-boot
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154 lines
4.2 KiB
C
154 lines
4.2 KiB
C
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/rtc.h>
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
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#if !defined(CONFIG_CF_SBF)
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/* Workaround, must place before fbcs */
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pll->psr = 0x12;
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scm1->mpr = 0x77777777;
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scm1->pacra = 0;
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scm1->pacrb = 0;
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scm1->pacrc = 0;
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scm1->pacrd = 0;
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scm1->pacre = 0;
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scm1->pacrf = 0;
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scm1->pacrg = 0;
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scm1->pacri = 0;
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
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&& defined(CONFIG_SYS_CS0_CTRL))
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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#endif
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#endif /* CONFIG_CF_SBF */
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
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&& defined(CONFIG_SYS_CS1_CTRL))
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
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&& defined(CONFIG_SYS_CS2_CTRL))
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
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&& defined(CONFIG_SYS_CS3_CTRL))
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
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&& defined(CONFIG_SYS_CS4_CTRL))
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
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&& defined(CONFIG_SYS_CS5_CTRL))
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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#endif
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#ifdef CONFIG_FSL_I2C
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gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFRTC
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volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
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u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR;
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rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
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rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
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#endif
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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gpio->par_uart &=
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(GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
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gpio->par_uart |=
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(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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break;
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case 1:
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gpio->par_uart &=
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(GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
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gpio->par_uart |=
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(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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break;
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case 2:
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gpio->par_dspi &=
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(GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
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gpio->par_dspi =
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(GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
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break;
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}
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}
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