mirror of
https://github.com/AsahiLinux/u-boot
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ddb56f371a
Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
223 lines
6.3 KiB
C
223 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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* Copyright 2022 Linaro
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*/
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#ifndef __IMX8MP_RSB3720_H
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#define __IMX8MP_RSB3720_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#include <config_distro_bootcmd.h>
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#define CONFIG_HAS_ETH1
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#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
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#define CONFIG_SPL_MAX_SIZE (152 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x960000
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#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
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#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
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#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
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* GD_FLG_FULL_MALLOC_INIT \
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* set \
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*/
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_DMA
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#define CONFIG_SPL_NAND_MXS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_IDENT
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of \
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* first 64MB boot area \
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*/
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/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
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* boot image (not only FIT part) to the mtdpart, so we check both two offsets
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
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(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
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#endif
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#endif
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#define CONFIG_REMAKE_ELF
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/* ENET Config */
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/* ENET1 */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define FEC_QUIRK_ENET_MAC
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#define DWC_NET_PHYADDR 4
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#ifdef CONFIG_DWC_ETH_QOS
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#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
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#endif
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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#if CONFIG_IS_ENABLED(CMD_MMC)
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# define BOOT_TARGET_MMC(func) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 1)
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#else
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# define BOOT_TARGET_MMC(func)
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#endif
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#if CONFIG_IS_ENABLED(CMD_PXE)
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# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
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#else
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# define BOOT_TARGET_PXE(func)
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#endif
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#if CONFIG_IS_ENABLED(CMD_DHCP)
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# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
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#else
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# define BOOT_TARGET_DHCP(func)
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#endif
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#define BOOT_TARGET_DEVICES(func) \
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BOOT_TARGET_MMC(func) \
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BOOT_TARGET_PXE(func) \
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BOOT_TARGET_DHCP(func)
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"script=boot.scr\0" \
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"image=Image\0" \
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"splashimage=0x50000000\0" \
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"console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
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"fdt_addr=0x43000000\0" \
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"fdt_addr_r=0x43000000\0" \
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"boot_fit=no\0" \
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"dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"kernel_addr_r=0x40480000\0" \
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"pxefile_addr_r=0x40480000\0" \
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"ramdisk_addr_r=0x43800000\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0" \
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"netargs=setenv bootargs ${jh_clk} console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0"
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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/* Totally 6GB or 4G DDR */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
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#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
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#define PHYS_SDRAM_2 0x100000000
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#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
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#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
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#define PHYS_SDRAM_2 0xC0000000
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#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
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#endif
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#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_IMX_BOOTAUX
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#ifdef CONFIG_FSL_FSPI
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#define FSL_FSPI_FLASH_SIZE SZ_32M
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#define FSL_FSPI_FLASH_NUM 1
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#define FSPI0_BASE_ADDR 0x30bb0000
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#define FSPI0_AMBA_BASE 0x0
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#define CONFIG_FSPI_QUAD_SUPPORT
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#define CONFIG_SYS_FSL_FSPI_AHB
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#endif
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#ifdef CONFIG_NAND_MXS
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/* NAND stuff */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x20000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#endif /* CONFIG_NAND_MXS */
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif /* __IMX8MP_RSB3720_H */
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