u-boot/arch/arm/cpu/armv7/omap5
Lokesh Vutla d4d986ee27 ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
..
config.mk omap5: Add minimal support for omap5430. 2011-11-15 22:25:50 +01:00
emif.c omap5: emif: Add emif/ddr configurations required for omap5 evm 2011-11-15 22:25:50 +01:00
hw_data.c ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs 2013-03-11 11:06:10 -04:00
hwinit.c ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup 2013-03-11 11:06:11 -04:00
Makefile ARM: OMAP4+: Clean up the pmic code 2013-03-11 11:06:10 -04:00
prcm-regs.c ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup 2013-03-11 11:06:11 -04:00
sdram.c ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs 2013-03-11 11:06:10 -04:00