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Biwen Li 164941c2c4 net: pfe_eth: read PFE ESBC header flash with spi_flash_read API 
Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
  Net:   SF: Detected s25fs512s with page size 256 Bytes, erase size 256
  KiB, total 64 MiB
  "Synchronous Abort" handler, esr 0x96000210
  elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
  elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
  x0 : 00000000b79407e8 x1 : 0000000040640000
  x2 : 0000000000000050 x3 : 0000000000000000
  x4 : 000000000000000a x5 : 0000000000000050
  x6 : 0000000000000366 x7 : 00000000b7942308
  x8 : 00000000b76407c0 x9 : 0000000000000008
  x10: 0000000000000044 x11: 00000000b7634d1c
  x12: 000000000000004f x13: 0000000000000044
  x14: 00000000b7634d98 x15: 00000000b76407c0
  x16: 0000000000000000 x17: 0000000000000000
  x18: 00000000b7636dd8 x19: 0000000000000000
  x20: 00000000b79407d0 x21: 00000000b79407e8
  x22: 0000000040640000 x23: 00000000b7634e58
  x24: 0000000000000000 x25: 0000000003800000
  x26: 00000000b7bdd000 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000b7634d10

  Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
  Resetting CPU ...

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
..
eth.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
Kconfig net: pfe_eth: read PFE ESBC header flash with spi_flash_read API 2020-12-10 13:56:39 +05:30
ls1012afrdm.c treewide: convert bd_t to struct bd_info by coccinelle 2020-07-17 09:30:13 -04:00
MAINTAINERS Add TFA boot flow for some Layerscape platforms 2018-12-10 17:19:59 -05:00
Makefile board: freescale: ls1012afrdm: enable network support on ls1012afrdm 2018-03-22 15:05:29 -05:00
README armv8: ls1012a: Add support of ls1012afrdm board 2016-06-03 14:12:51 -07:00

README 

Overview
--------
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
platform, with a complete debugging environment. The LS1012AFRDM board
supports the QorIQ LS1012A processor and is optimized to support the
high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.

 LS1012AFRDM board Overview
 -----------------------
 - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
     - 2 SGMII 1G PHYs
 - DDR Controller
     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
	operating at 1.35 V
 - QSPI
     - Onboard 512 Mbit QSPI flash memory running at speed up
      to 108/54 MHz
 - One high-speed USB 2.0/3.0 port, one USB 2.0 port
     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
       Micro-AB connector.
     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
       as a Micro-AB device.
 - I2C controller
     - One I2C bus with connectivity to Arduino headers
 - UART
     - UART (Console): UART1 (Without flow control) for console
 - ARM JTAG support
     - ARM Cortex® 10-pin JTAG connector for LS1012A
     - CMSIS DAP through K20 microcontroller
 - SAI Audio interface
     - One SAI port, SAI 2 with full duplex support
 - Clocks
     - 25 MHz crystal for LS1012A
     - 8 MHz Crystal for K20
     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
 - Power Supplies
     - 5 V input supply from USB
     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
       other board interfaces

Booting Options
---------------
QSPI Flash 1

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot 		| 1MB	| 0x4010_0000
U-boot Env 	| 1MB	| 0x4020_0000
PPA FIT image	| 2MB	| 0x4050_0000
Linux ITB	| ~53MB | 0x40A0_0000