board: freescale: ls1012afrdm: enable network support on ls1012afrdm

This patch enables ethernet support for ls1012afrdm.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Calvin Johnson 2018-03-08 15:30:29 +05:30 committed by Joe Hershberger
parent 7a8df8ba33
commit a141f33af5
4 changed files with 154 additions and 5 deletions

View file

@ -12,6 +12,35 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012afrdm"
if FSL_PFE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select PHYLIB
imply PHY_REALTEK
config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
default 0x03800000
config DDR_PFE_BASEADDR
hex "PFE DDR base address"
default 0x83800000
config PFE_EMAC1_PHY_ADDR
hex "PFE DDR base address"
default 0x2
config PFE_EMAC2_PHY_ADDR
hex "PFE DDR base address"
default 0x1
endif
source "board/freescale/common/Kconfig"
endif

View file

@ -5,3 +5,4 @@
#
obj-y += ls1012afrdm.o
obj-$(CONFIG_FSL_PFE) += eth.o

View file

@ -0,0 +1,124 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <netdev.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/types.h>
#include <fsl_dtsec.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/config.h>
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
#include <asm/arch/fsl_serdes.h>
#include <net/pfe_eth/pfe_eth.h>
#include <dm/platform_data/pfe_dm_eth.h>
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
#define MASK_ETH_PHY_RST 0x00000100
static inline void ls1012afrdm_reset_phy(void)
{
unsigned int val;
struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
val = in_be32(&pgpio->gpdat);
setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
mdelay(10);
val = in_be32(&pgpio->gpdat);
setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
mdelay(50);
}
int pfe_eth_board_init(struct udevice *dev)
{
static int init_done;
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
if (!init_done) {
ls1012afrdm_reset_phy();
mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
bus = pfe_mdio_init(&mac_mdio_info);
if (!bus) {
printf("Failed to register mdio\n");
return -1;
}
init_done = 1;
}
if (priv->gemac_port) {
mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
bus = pfe_mdio_init(&mac_mdio_info);
if (!bus) {
printf("Failed to register mdio\n");
return -1;
}
}
pfe_set_mdio(priv->gemac_port,
miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
if (!priv->gemac_port)
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII);
else
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII);
return 0;
}
static struct pfe_eth_pdata pfe_pdata0 = {
.pfe_eth_pdata_mac = {
.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
.phy_interface = 0,
},
.pfe_ddr_addr = {
.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
},
};
static struct pfe_eth_pdata pfe_pdata1 = {
.pfe_eth_pdata_mac = {
.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
.phy_interface = 1,
},
.pfe_ddr_addr = {
.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
},
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
.platdata = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
.platdata = &pfe_pdata1,
};

View file

@ -57,11 +57,6 @@ int dram_init(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();