mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
68 lines
1.2 KiB
C
68 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 Arm Limited
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* Usama Arif <usama.arif@arm.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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static const struct pl01x_serial_plat serial_plat = {
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.base = UART0_BASE,
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.type = TYPE_PL011,
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.clock = CONFIG_PL011_CLOCK,
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};
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U_BOOT_DRVINFO(total_compute_serials) = {
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.name = "serial_pl01x",
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.plat = &serial_plat,
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};
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static struct mm_region total_compute_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0xff80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = total_compute_mem_map;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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/* Nothing to be done here as handled by PSCI interface */
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void reset_cpu(void)
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{
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}
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