mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
891ab74b1f
Commit6aa4ad8e38("Convert CONFIG_SOC_DA8XX et al to Kconfig") converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for SOC_DA8XX, which broke OMAPL138 to boot. Commit2e87980580("davinci: Fix omapl138_lcdk builds") disabled DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot as ddr is not being initialized. Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138 will have ddr initialized Fixes:2e87980580("davinci: Fix omapl138_lcdk builds") Fixes:6aa4ad8e38("Convert CONFIG_SOC_DA8XX et al to Kconfig") Reported-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Tom Rini <trini@konsulko.com>
159 lines
3 KiB
Text
159 lines
3 KiB
Text
if ARCH_DAVINCI
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choice
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prompt "DaVinci board select"
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optional
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config TARGET_IPAM390
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bool "IPAM390 board"
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select MACH_DAVINCI_DA850_EVM
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select SOC_DA850
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select SUPPORT_SPL
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config TARGET_DA850EVM
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bool "DA850 EVM board"
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select MACH_DAVINCI_DA850_EVM
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select SOC_DA850
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select SUPPORT_SPL
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config TARGET_EA20
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bool "EA20 board"
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select MACH_DAVINCI_DA850_EVM
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select SOC_DA850
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select BOARD_LATE_INIT
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config TARGET_OMAPL138_LCDK
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bool "OMAPL138 LCDK"
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select SOC_DA8XX
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select SUPPORT_SPL
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config TARGET_CALIMAIN
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bool "Calimain board"
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select SOC_DA850
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config TARGET_LEGOEV3
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bool "LEGO MINDSTORMS EV3"
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select MACH_DAVINCI_DA850_EVM
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select SOC_DA850
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endchoice
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config SYS_SOC
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default "davinci"
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config DA850_LOWLEVEL
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bool "Enable Lowlevel DA850 initialization"
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depends on SOC_DA850
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config SYS_DA850_PLL_INIT
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bool
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config SYS_DA850_DDR_INIT
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bool
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config SOC_DA850
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bool
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select SOC_DA8XX
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config SOC_DA8XX
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bool
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select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
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select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
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config MACH_DAVINCI_DA850_EVM
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bool
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if SYS_DA850_PLL_INIT
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comment "DA850 PLL Initialization Parameters"
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config SYS_DV_CLKMODE
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int "PLLCTL Clock Mode"
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default 0
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help
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Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
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config SYS_DA850_PLL0_POSTDIV
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int "PLLC0 PLL Post-Divider"
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default 1
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help
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Value written to PLLC0 PLL Post-Divider Control Register
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config SYS_DA850_PLL0_PLLDIV1
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hex "PLLC0 Divider 1"
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default 0x8000
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help
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Value written to PLLC0 Divider 1 register
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config SYS_DA850_PLL0_PLLDIV2
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hex "PLLC0 Divider 2"
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default 0x8001
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help
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Value written to PLLC0 Divider 2 register
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config SYS_DA850_PLL0_PLLDIV3
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hex "PLLC0 Divider 3"
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default 0x8002
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help
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Value written to PLLC0 Divider 3 register
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config SYS_DA850_PLL0_PLLDIV4
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hex "PLLC0 Divider 4"
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default 0x8003
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help
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Value written to PLLC0 Divider 4 register
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config SYS_DA850_PLL0_PLLDIV5
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hex "PLLC0 Divider 5"
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default 0x8002
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help
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Value written to PLLC0 Divider 5 register
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config SYS_DA850_PLL0_PLLDIV6
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hex "PLLC0 Divider 6"
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default 0x8000
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help
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Value written to PLLC0 Divider 6 register
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config SYS_DA850_PLL0_PLLDIV7
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hex "PLLC0 Divider 7"
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default 0x8005
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help
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Value written to PLLC0 Divider 7 register
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config SYS_DA850_PLL1_POSTDIV
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hex "PLLC1 PLL Post-Divider"
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default 1
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help
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Value written to PLLC1 PLL Post-Divider Control Register
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config SYS_DA850_PLL1_PLLDIV1
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hex "PLLC1 Divider 2"
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default 0x8000
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help
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Value written to PLLC1 Divider 1 register
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config SYS_DA850_PLL1_PLLDIV2
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hex "PLLC1 Divider 2"
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default 0x8001
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help
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Value written to PLLC1 Divider 2 register
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config SYS_DA850_PLL1_PLLDIV3
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hex "PLLC1 Divider 3"
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default 0x8002
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help
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Value written to PLLC1 Divider 3 register
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endif
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source "board/Barix/ipam390/Kconfig"
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source "board/davinci/da8xxevm/Kconfig"
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source "board/davinci/ea20/Kconfig"
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source "board/omicron/calimain/Kconfig"
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source "board/lego/ev3/Kconfig"
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config SPL_LDSCRIPT
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default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
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default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
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endif
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