mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
060f9bf57b
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
14 lines
199 B
C
14 lines
199 B
C
/*
|
|
* (C) Copyright 2012,2015 Stephen Warren
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#ifndef __CONFIG_H
|
|
#define __CONFIG_H
|
|
|
|
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
|
|
#include "rpi-common.h"
|
|
|
|
#endif
|