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ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

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The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
This commit is contained in:
Alexander Stein 2015-07-24 09:22:11 +02:00 committed by Tom Rini
parent 2085ae74de
commit 060f9bf57b
2 changed files with 3 additions and 0 deletions
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2
include/configs/rpi.h
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@ -7,6 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 32
#include "rpi-common.h"
#endif

1
include/configs/rpi_2.h
View file

@ -9,6 +9,7 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BCM2836
#define CONFIG_SYS_CACHELINE_SIZE 64
#include "rpi-common.h"