u-boot/arch/mips
Paul Burton cc4f36435f MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
..
cpu MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds 2017-11-28 21:59:30 +01:00
dts mips: bmips: fix BCM3380 periph clock frequency 2017-05-31 15:45:29 +02:00
include/asm MIPS: Clear instruction hazards in flush_cache() 2017-11-28 21:59:30 +01:00
lib MIPS: Break out of cache loops for unimplemented caches 2017-11-28 21:59:30 +01:00
mach-ath79 board_f: Rename initdram() to dram_init() 2017-04-13 09:40:57 -04:00
mach-au1x00 Fix spelling of "resetting". 2016-10-31 10:13:17 -04:00
mach-bmips mips: bmips: add board descriptions 2017-05-31 14:49:55 +02:00
mach-pic32 board_f: Rename initdram() to dram_init() 2017-04-13 09:40:57 -04:00
config.mk MIPS: Stop building position independent code 2017-07-25 20:44:00 +02:00
Kconfig env: Convert CONFIG_ENV_IS_IN... to a choice 2017-08-15 20:50:01 -04:00
Makefile MIPS: add initial infrastructure for Broadcom MIPS SoCs 2017-05-10 16:16:09 +02:00
Makefile.postlink MIPS: Stop building position independent code 2017-07-25 20:44:00 +02:00