mirror of
https://github.com/AsahiLinux/u-boot
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8564acf936
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
(8270/8275/8280)
* Patch by Bernhard Kuhn, 08 Jul 2003:
- add support for M68K targets
* Patch by Ken Chou, 3 Jul:
- Fix PCI config table for A3000
- Fix iobase for natsemi.c
(PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
307 lines
9.7 KiB
C
307 lines
9.7 KiB
C
/*
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* (C) Copyright 2001
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* Stuart Hughes <stuarth@lineo.com>
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* This file is based on similar values for other boards found in other
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* U-Boot config files, and some that I found in the mpc8260ads manual.
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*
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* Note: my board is a PILOT rev.
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* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Added support for SDRAM DIMMs SPD EEPROM, MII.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */
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#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
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/* allow serial and ethaddr to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#ifdef CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers (see 28-13)
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* - Full duplex
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_INDEX */
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 2 /* Port C */
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#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
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#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
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#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
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else iop->pdat &= ~0x00400000
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#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
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else iop->pdat &= ~0x00200000
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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/* other options */
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
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#define CONFIG_SPD_ADDR 0x50
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#endif
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#ifndef CONFIG_SDRAM_PBI
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#define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */
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#endif
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66666666 /* in Hz */
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
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CFG_CMD_BEDBUG | \
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CFG_CMD_BMP | \
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CFG_CMD_BSP | \
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CFG_CMD_DATE | \
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CFG_CMD_DOC | \
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CFG_CMD_DTT | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_FDC | \
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CFG_CMD_FDOS | \
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CFG_CMD_HWFLOW | \
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CFG_CMD_IDE | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_KGDB | \
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CFG_CMD_MMC | \
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CFG_CMD_NAND | \
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CFG_CMD_PCI | \
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CFG_CMD_PCMCIA | \
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CFG_CMD_SCSI | \
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CFG_CMD_SPI | \
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CFG_CMD_VFD | \
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CFG_CMD_USB ) )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#endif
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_FLASH_BASE 0xff800000
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#define FLASH_BASE 0xff800000
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
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#define CFG_FLASH_SIZE 8
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
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#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#define CFG_JFFS2_FIRST_SECTOR 1
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#define CFG_JFFS2_LAST_SECTOR 27
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#define CFG_JFFS2_SORT_FRAGMENTS
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#define CFG_JFFS_CUSTOM_PART
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/* this is stuff came out of the Motorola docs */
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#define CFG_DEFAULT_IMMR 0x0F010000
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#define CFG_IMMR 0xF0000000
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#define CFG_BCSR 0x04500000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_LSDRAM_BASE 0x04000000
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#define RS232EN_1 0x02000002
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#define RS232EN_2 0x01000001
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#define FETHIEN 0x08000008
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#define FETH_RST 0x04000004
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* 0x0EA28205 */
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#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
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( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
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( HRCW_BMS | HRCW_APPC10 ) |\
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( HRCW_MODCK_H0101 ) \
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)
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#ifndef CFG_RAMBOOT
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# define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_SECT_SIZE 0x40000
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
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#else
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# define CFG_ENV_IS_IN_NVRAM 1
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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# define CFG_ENV_SIZE 0x200
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#endif /* CFG_RAMBOOT */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
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#define CFG_HID2 0
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#define CFG_SYPCR 0xFFFFFFC3
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#define CFG_BCR 0x100C0000
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#define CFG_SIUMCR 0x0A200000
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#define CFG_SCCR 0x00000000
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#define CFG_BR0_PRELIM 0xFF801801
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#define CFG_OR0_PRELIM 0xFF800836
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#define CFG_BR1_PRELIM 0x04501801
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#define CFG_OR1_PRELIM 0xFFFF8010
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#define CFG_RMR 0
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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#define CFG_RCCR 0
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#define CFG_PSDMR 0x016EB452
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#define CFG_MPTPR 0x00001900
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#define CFG_PSRT 0x00000021
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#define CFG_RESET_ADDRESS 0x04400000
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#endif /* __CONFIG_H */
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