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* Patches by Yuli Barcohen, 13 Jul 2003:

Browse source 
- Correct flash and JFFS2 support for MPC8260ADS
  - fix PVR values and clock generation for PowerQUICC II family
    (8270/8275/8280)

* Patch by Bernhard Kuhn, 08 Jul 2003:
  - add support for M68K targets

* Patch by Ken Chou, 3 Jul:
  - Fix PCI config table for A3000
  - Fix iobase for natsemi.c
    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)

* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
This commit is contained in:
wdenk 2003-07-14 22:13:32 +00:00
parent 5702923e23
commit 8564acf936
40 changed files with 818 additions and 445 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
CHANGELOG
View file

@ -1,13 +1,34 @@
======================================================================
Changes for U-Boot 0.4.2:
Changes for U-Boot 0.4.3:
======================================================================
* Patches by Yuli Barcohen, 13 Jul 2003:
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
(8270/8275/8280)
* Patch by Bernhard Kuhn, 08 Jul 2003:
- add support for M68K targets
* Patch by Ken Chou, 3 Jul:
- Fix PCI config table for A3000
- Fix iobase for natsemi.c
(PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
* Patch by Stefan Roese, 11 Jul 2003:
- Fix bug in CONFIG_VERSION_VARIABLE.
- AR405 config updated.
- OCRTC/ORSG: bsp command added.
- ASH405 bsp update.
======================================================================
Changes for U-Boot 0.4.2:
======================================================================
* Add support for NSCU board
* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules

1
MAINTAINERS
View file

@ -72,7 +72,6 @@ Wolfgang Denk <wd@denx.de>
TQM855L MPC855
TQM860L MPC860
TQM860L_FEC MPC860
TTTech MPC823
c2mon MPC855
hermes MPC860
lwmon MPC823

2
MAKEALL
View file

@ -36,7 +36,7 @@ LIST_8xx=" \
rmu RPXClassic RPXlite RRvision \
SM850 SPD823TS svm_sc8xx SXNI855T \
TOP860 TQM823L TQM823L_LCD TQM850L \
TQM855L TQM860L TTTech v37 \
TQM855L TQM860L v37 \
"
#########################################################################

10
README
View file

@ -1481,6 +1481,16 @@ Configuration Settings:
- CFG_FLASH_WRITE_TOUT:
Timeout for Flash write operations (in ms)
- CFG_FLASH_LOCK_TOUT
Timeout for Flash set sector lock bit operation (in ms)
- CFG_FLASH_UNLOCK_TOUT
Timeout for Flash clear lock bits operation (in ms)
- CFG_FLASH_PROTECTION
If defined, hardware flash sectors protection is used
instead of U-Boot software protection.
- CFG_DIRECT_FLASH_TFTP:
Enable TFTP transfers directly to flash memory;

68
board/RRvision/video_ad7179.h Normal file
View file

@ -0,0 +1,68 @@
/*
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define VIDEO_ENCODER_NAME "Analog Devices AD7179"
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
#undef VIDEO_MODE_RGB
#define VIDEO_MODE_BPP 16
#ifdef VIDEO_MODE_PAL
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 576
#define VIDEO_VISIBLE_COLS 640
#define VIDEO_VISIBLE_ROWS 480
#else
#error "NTSC mode is not supported"
#endif
static unsigned char video_encoder_data[] = {
0x05, /* Mode Register 0 */
0x11, /* Mode Register 1 */
0x20, /* Mode Register 2 */
0x0C, /* Mode Register 3 */
0x01, /* Mode Register 4 */
0x00, /* Reserved */
0x00, /* Reserved */
0x04, /* Timing Register 0 */
0x00, /* Timing Register 1 */
0xCB, /* Subcarrier Frequency Register 0 */
0x0A, /* Subcarrier Frequency Register 1 */
0x09, /* Subcarrier Frequency Register 2 */
0x2A, /* Subcarrier Frequency Register 3 */
0x00, /* Subcarrier Phase */
0x00, /* Closed Captioning Ext Reg 0 */
0x00, /* Closed Captioning Ext Reg 1 */
0x00, /* Closed Captioning Reg 0 */
0x00, /* Closed Captioning Reg 1 */
0x00, /* Pedestal Control Reg 0 */
0x00, /* Pedestal Control Reg 1 */
0x00, /* Pedestal Control Reg 2 */
0x00, /* Pedestal Control Reg 3 */
0x00, /* CGMS_WSS Reg 0 */
0x00, /* CGMS_WSS Reg 0 */
0x00, /* CGMS_WSS Reg 0 */
0x00 /* Teletext Req. Control Reg */
} ;

39
board/a3000/a3000.c
View file

@ -2,6 +2,9 @@
* (C) Copyright 2001
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* Modified during 2003 by
* Ken Chou, kchou@ieee.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -86,52 +89,42 @@ Done:
/*
* Initialize PCI Devices
*/
#if 1
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_a3000_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0x0, 0x0, 0x0, /* unknown eth0 divice */
/* vendor, device, class */
/* bus, dev, func */
{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0x0, 0x0, 0x0, /* unknown eth1 device */
PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
PCI_ENET1_MEMADDR,
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0x0, 0x0, 0x0, /* unknown eth1 device */
PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
PCI_ENET2_MEMADDR,
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
PCI_ENET3_MEMADDR,
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER }},
{ }
};
#endif
#else
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_a3000_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
PCI_ENET1_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
#endif
#endif
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_a3000_config_table,

11
board/gen860t/gen860t.c
View file

@ -302,4 +302,15 @@ board_poweroff(void)
while (1);
}
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif
/* vim: set ts=4 sw=4 tw=78 : */

22
board/lwmon/lwmon.c
View file

@ -184,7 +184,7 @@ V* Verification: dzu@denx.de
***********************************************************************/
int checkboard (void)
{
puts ("Board: Litronic Monitor IV\n");
puts ("Board: LICCON Konsole LCD2\n");
return (0);
}
@ -1071,3 +1071,23 @@ static int key_pressed(void)
return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
}
#endif /* CONFIG_MODEM_SUPPORT */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(gd_t *gd)
{
uchar kbd_data[KEYBD_DATALEN];
uchar val;
/* Read keys */
val = KEYBD_CMD_READ_KEYS;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
return (gd->post_hotkeys_latch =
(compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
}
#endif

496
board/mpc8260ads/flash.c
View file

@ -7,6 +7,11 @@
* I started with board/ip860/flash.c and made changes I found in
* the MTD project by David Schleef.
*
* (C) Copyright 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
* Re-written to support multi-bank flash SIMMs.
* Added support for real protection and JFFS2.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -28,73 +33,119 @@
#include <common.h>
/* Intel-compatible flash ID */
#define INTEL_COMPAT 0x89898989
#define INTEL_ALT 0xB0B0B0B0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Intel-compatible flash commands */
#define INTEL_PROGRAM 0x10101010
#define INTEL_ERASE 0x20202020
#define INTEL_CLEAR 0x50505050
#define INTEL_LOCKBIT 0x60606060
#define INTEL_PROTECT 0x01010101
#define INTEL_STATUS 0x70707070
#define INTEL_READID 0x90909090
#define INTEL_CONFIRM 0xD0D0D0D0
#define INTEL_RESET 0xFFFFFFFF
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
/* Intel-compatible flash status bits */
#define INTEL_FINISHED 0x80808080
#define INTEL_OK 0x80808080
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
* This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
* Up to 32MB of flash supported (up to 4 banks.)
* BCSR is used for flash presence detect (page 4-65 of the User's Manual)
*
* The following code can not run from flash!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
#ifndef CONFIG_MPC8260ADS
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
#endif
unsigned long size;
int i;
ulong size = 0, sect_start, sect_size = 0, bank_size;
ushort sect_count = 0;
int i, j, nbanks;
vu_long *addr = (vu_long *)CFG_FLASH_BASE;
vu_long *bcsr = (vu_long *)CFG_BCSR;
/* Init: enable write,
* or we cannot even write flash commands
*/
#ifndef CONFIG_MPC8260ADS
bcsr->bd_ctrl |= BD_CTRL_FLWE;
#endif
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
switch (bcsr[2] & 0xF) {
case 0:
nbanks = 4;
break;
case 1:
nbanks = 2;
break;
case 2:
nbanks = 1;
break;
default: /* Unsupported configurations */
nbanks = CFG_MAX_FLASH_BANKS;
}
/* Static FLASH Bank configuration here - FIXME XXX */
if (nbanks > CFG_MAX_FLASH_BANKS)
nbanks = CFG_MAX_FLASH_BANKS;
size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
for (i = 0; i < nbanks; i++) {
*addr = INTEL_READID; /* Read Intelligent Identifier */
if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
switch (addr[1]) {
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
sect_count = 32;
sect_size = 0x40000;
break;
default:
flash_info[i].flash_id = FLASH_UNKNOWN;
sect_count = CFG_MAX_FLASH_SECT;
sect_size =
CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
}
}
else
flash_info[i].flash_id = FLASH_UNKNOWN;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
addr[0], addr[1], (ulong)addr);
size = 0;
*addr = INTEL_RESET; /* Reset bank to Read Array mode */
break;
}
flash_info[i].sector_count = sect_count;
flash_info[i].size = bank_size = sect_size * sect_count;
size += bank_size;
sect_start = (ulong)addr;
for (j = 0; j < sect_count; j++) {
addr = (vu_long *)sect_start;
flash_info[i].start[j] = sect_start;
flash_info[i].protect[j] = (addr[2] == 0x01010101);
sect_start += sect_size;
}
*addr = INTEL_RESET; /* Reset bank to Read Array mode */
addr = (vu_long *)sect_start;
}
#ifndef CONFIG_MPC8260ADS
/* Remap FLASH according to real size */
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
(memctl->memc_br1 & ~(BR_BA_MSK));
#endif
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
if (size == 0) { /* Unknown flash, fill with hard-coded values */
sect_start = CFG_FLASH_BASE;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
flash_info[i].sector_count = sect_count;
for (j = 0; j < sect_count; j++) {
flash_info[i].start[j] = sect_start;
flash_info[i].protect[j] = 0;
sect_start += sect_size;
}
}
size = CFG_FLASH_SIZE;
}
else
for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].size = 0;
flash_info[i].sector_count = 0;
}
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
@ -161,102 +212,6 @@ void flash_print_info (flash_info_t *info)
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
ulong sector_offset;
/* Write "Intelligent Identifier" command: read Manufacturer ID */
*addr = 0x90909090;
value = addr[0] & 0x00FF00FF;
switch (value) {
case MT_MANUFACT: /* SHARP, MT or => Intel */
case INTEL_ALT_MANU:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf("unknown manufacturer: %x\n", (unsigned int)value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
switch (value) {
case (INTEL_ID_28F016S):
info->flash_id += FLASH_28F016SV;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F160S3):
info->flash_id += FLASH_28F160S3;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F320S3):
info->flash_id += FLASH_28F320S3;
info->sector_count = 64;
info->size = 0x00800000;
sector_offset = 0x20000;
break; /* => 2x4 MB */
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
info->sector_count = 32;
info->size = 0x00800000;
sector_offset = 0x40000;
break; /* => 4x2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += sector_offset;
/* don't know how to check sector protection */
info->protect[i] = 0;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
*addr = 0xFFFFFF; /* reset bank to read array mode */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
@ -292,12 +247,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
printf ("\n");
}
/* Make Sure Block Lock Bit is not set. */
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
return 1;
}
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
@ -308,36 +257,26 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Reset Array */
*addr = 0xffffffff;
/* Clear Status Register */
*addr = 0x50505050;
*addr = INTEL_CLEAR;
/* Single Block Erase Command */
*addr = 0x20202020;
*addr = INTEL_ERASE;
/* Confirm */
*addr = 0xD0D0D0D0;
*addr = INTEL_CONFIRM;
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
/* Resume Command, as per errata update */
*addr = 0xD0D0D0D0;
*addr = INTEL_CONFIRM;
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x80808080) != 0x80808080) {
if(*addr & 0x20202020){
printf("Error in Block Erase - Lock Bit may be set!\n");
printf("Status Register = 0x%X\n", (uint)*addr);
*addr = 0xFFFFFFFF; /* reset bank */
return 1;
}
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
*addr = INTEL_RESET; /* reset bank */
return 1;
}
/* show that we're waiting */
@ -347,8 +286,15 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
if (*addr != INTEL_OK) {
printf("Block erase failed at %08X, CSR=%08X\n",
(uint)addr, (uint)*addr);
*addr = INTEL_RESET; /* reset bank */
return 1;
}
/* reset to read mode */
*addr = 0xFFFFFFFF;
*addr = INTEL_RESET;
}
}
@ -356,6 +302,58 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
return 0;
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
ulong start;
int rc = 0;
int flag;
vu_long *addr = (vu_long *)dest;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
}
*addr = INTEL_CLEAR; /* Clear status register */
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = INTEL_PROGRAM;
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
printf("Write timed out\n");
rc = 1;
break;
}
}
if (*addr != INTEL_OK) {
printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
rc = 1;
}
*addr = INTEL_RESET; /* Reset to read array mode */
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
@ -370,6 +368,8 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
wp = (addr & ~3); /* get lower word aligned address */
*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
/*
* handle unaligned start bytes
*/
@ -424,85 +424,125 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
rc = write_word(info, wp, data);
return rc;
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* Set/Clear sector's lock bit, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 1 - Error (timeout, voltage problems, etc.)
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
int flash_real_protect(flash_info_t *info, long sector, int prot)
{
vu_long *addr = (vu_long *)dest;
ulong start, csr;
int flag;
ulong start;
int i;
int rc = 0;
vu_long *addr = (vu_long *)(info->start[sector]);
int flag = disable_interrupts();
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
*addr = INTEL_CLEAR; /* Clear status register */
if (prot) { /* Set sector lock bit */
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
}
else { /* Clear sector lock bit */
*addr = INTEL_LOCKBIT; /* All sectors lock bits */
*addr = INTEL_CONFIRM; /* clear */
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = 0x10101010;
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x80808080) != 0x80808080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
flag = 1;
start = get_timer(0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
printf("Flash lock bit operation timed out\n");
rc = 1;
break;
}
}
if (csr & 0x40404040) {
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
if (*addr != INTEL_OK) {
printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
(uint)addr, (uint)*addr);
rc = 1;
}
/* Clear Status Registers Command */
*addr = 0x50505050;
/* Reset to read array mode */
*addr = 0xFFFFFFFF;
if (!rc)
info->protect[sector] = prot;
return (flag);
/*
* Clear lock bit command clears all sectors lock bits, so
* we have to restore lock bits of protected sectors.
*/
if (!prot)
for (i = 0; i < info->sector_count; i++)
if (info->protect[i]) {
addr = (vu_long *)(info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
udelay(CFG_FLASH_LOCK_TOUT * 1000);
}
if (flag)
enable_interrupts();
*addr = INTEL_RESET; /* Reset to read array mode */
return rc;
}
/*-----------------------------------------------------------------------
* Clear Block Lock Bit, returns:
* 0 - OK
* 1 - Timeout
* Support for flash file system (JFFS2)
*
* We use custom partition info function because we have to fit the
* file system image between first sector (containing hard reset
* configuration word) and the sector containing U-Boot image. Standard
* partition info function does not allow for last sector specification
* and assumes that the file system occupies flash bank up to and
* including bank's last sector.
*/
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
static int clear_block_lock_bit(vu_long * addr)
#ifndef CFG_JFFS2_FIRST_SECTOR
#define CFG_JFFS2_FIRST_SECTOR 0
#endif
#ifndef CFG_JFFS2_FIRST_BANK
#define CFG_JFFS2_FIRST_BANK 0
#endif
#ifndef CFG_JFFS2_NUM_BANKS
#define CFG_JFFS2_NUM_BANKS 1
#endif
#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
#include <jffs2/jffs2.h>
static struct part_info partition;
struct part_info *jffs2_part_info(int part_num)
{
ulong start, now;
int i;
/* Reset Array */
*addr = 0xffffffff;
/* Clear Status Register */
*addr = 0x50505050;
if (part_num == 0) {
if (partition.usr_priv == 0) {
partition.offset =
(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
partition.size += flash_info[i].size;
partition.size -=
flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
flash_info[CFG_JFFS2_FIRST_BANK].start[0];
#ifdef CFG_JFFS2_LAST_SECTOR
i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
partition.size -=
flash_info[CFG_JFFS2_LAST_BANK].start[i] -
flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
#endif
*addr = 0x60606060;
*addr = 0xd0d0d0d0;
start = get_timer (0);
while(*addr != 0x80808080){
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
return 1;
partition.usr_priv = (void *)1;
}
return &partition;
}
return 0;
}
#endif /* JFFS2 */

12
board/sacsng/sacsng.c
View file

@ -816,3 +816,15 @@ int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
#endif /* CFG_CMD_SPI */
#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif

1
common/cmd_bootm.c
View file

@ -1024,6 +1024,7 @@ print_type (image_header_t *hdr)
case IH_CPU_SH: arch = "SuperH"; break;
case IH_CPU_SPARC: arch = "SPARC"; break;
case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break;
case IH_CPU_M68K: arch = "M68K"; break;
default: arch = "Unknown Architecture"; break;
}

11
cpu/mpc8260/commproc.c
View file

@ -111,9 +111,9 @@ m8260_cpm_hostalloc(uint size, uint align)
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
#define BRG_UART_CLK (BRG_INT_CLK / 16)
/* This function is used by UARTS, or anything else that uses a 16x
/* This function is used by UARTs, or anything else that uses a 16x
* oversampled clock.
*/
void
@ -123,9 +123,10 @@ m8260_cpm_setbrg(uint brg, uint rate)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
uint cd = BRG_UART_CLK / rate;
/* This is good enough to get SMCs running.....
*/
if ((BRG_UART_CLK % rate) < (rate / 2))
cd--;
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
}
@ -134,7 +135,7 @@ m8260_cpm_setbrg(uint brg, uint rate)
brg -= 4;
}
bp += brg;
*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
*bp = (cd << 1) | CPM_BRG_EN;
}
/* This function is used to set high speed synchronous baud rate

27
cpu/mpc8260/cpu.c
View file

@ -22,7 +22,7 @@
*/
/*
* CPU specific code for the MPC8255 / MPC8260 CPUs
* CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
*
* written or collected and sometimes rewritten by
* Magnus Damm <damm@bitsmart.com>
@ -35,6 +35,9 @@
*
* added 8260 masks by
* Marius Groeger <mag@sysgo.de>
*
* added HiP7 (8270/8275/8280) processors support by
* Yuli Barcohen <yuli@arabellasw.com>
*/
#include <common.h>
@ -56,15 +59,27 @@ int checkcpu (void)
puts ("CPU: ");
if (((pvr >> 16) & 0xff) != 0x81)
switch (pvr) {
case PVR_8260:
case PVR_8260_HIP3:
k = 3;
break;
case PVR_8260_HIP4:
k = 4;
break;
case PVR_8260_HIP7:
k = 7;
break;
default:
return -1; /* whoops! not an MPC8260 */
}
rev = pvr & 0xff;
immr = immap->im_memctl.memc_immr;
if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
return -1; /* whoops! someone moved the IMMR */
printf (CPU_ID_STR " (Rev %02x, Mask ", rev);
printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
/*
* the bottom 16 bits of the immr are the Part Number and Mask Number
@ -104,6 +119,12 @@ int checkcpu (void)
case 0x0062:
printf ("B.1 4K25A");
break;
case 0x0A00:
printf ("0.0 0K49M");
break;
case 0x0A01:
printf ("0.1 1K49M");
break;
default:
printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
break;

16
cpu/mpc8260/speed.c
View file

@ -120,15 +120,19 @@ int get_clocks (void)
scmr = immap->im_clkrst.car_scmr;
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
cp = &corecnf_tab[corecnf];
gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */
pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
gd->vco_out = clkin * (pllmf + 1);
} else { /* HiP3, HiP4 */
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
}
#if 0
if (gd->vco_out / (busdf + 1) != clkin) {
/* aaarrrggghhh!!! */

19
cpu/mpc8xx/lcd.c
View file

@ -25,6 +25,8 @@
/* ** HEADER FILES */
/************************************************************************/
/* #define DEBUG */
#include <config.h>
#include <common.h>
#include <watchdog.h>
@ -1057,6 +1059,23 @@ static void lcd_enable (void)
/* Now turn on LCD_ON */
immr->im_cpm.cp_pbdat |= 0x00001000;
#endif
#ifdef CONFIG_RRVISION
debug ("PC4->Output(1): enable LVDS\n");
debug ("PC5->Output(0): disable PAL clock\n");
immr->im_ioport.iop_pddir |= 0x1000;
immr->im_ioport.iop_pcpar &= ~(0x0C00);
immr->im_ioport.iop_pcdir |= 0x0C00 ;
immr->im_ioport.iop_pcdat |= 0x0800 ;
immr->im_ioport.iop_pcdat &= ~(0x0400);
debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
immr->im_ioport.iop_pdpar,
immr->im_ioport.iop_pddir,
immr->im_ioport.iop_pddat);
debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
immr->im_ioport.iop_pcpar,
immr->im_ioport.iop_pcdir,
immr->im_ioport.iop_pcdat);
#endif
}
/*----------------------------------------------------------------------*/

133
cpu/mpc8xx/video.c
View file

@ -23,7 +23,7 @@
* MA 02111-1307 USA
*/
/* #define DEBUG */
/* #define DEBUG */
/************************************************************************/
/* ** HEADER FILES */
@ -86,6 +86,14 @@
#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR
#endif
#ifdef CONFIG_VIDEO_ENCODER_AD7179
#include <video_ad7179.h> /* Sets encoder data, mode, and visible and active area */
#define VIDEO_I2C 1
#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR
#endif
/************************************************************************/
/* ** VIDEO MODE CONSTANTS */
/************************************************************************/
@ -155,7 +163,7 @@
/* ** CONSOLE CONSTANTS */
/************************************************************************/
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_LOGO
#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT)
#define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH)
#else
@ -163,11 +171,11 @@
#endif
#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH)
#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN)
#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN)
#define CONSOLE_ROW_FIRST (video_console_address)
#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE)
#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE)
#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE)
#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
/*
@ -287,8 +295,8 @@ static int video_maprgb (int r, int g, int b)
/* Calculate YUV values (0-255) from RGB beetween 0-100 */
YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16;
YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128;
YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128;
YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128;
YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128;
return *ret;
#endif
#ifdef VIDEO_MODE_RGB
@ -473,6 +481,7 @@ static inline void video_putstring (int xx, int yy, unsigned char *s)
/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */
/************************************************************************/
#if !defined(CONFIG_RRVISION)
static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
{
int i;
@ -485,6 +494,7 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
dest[0].lcyc++; /* Add a cycle to the first entry */
dest[entries - 1].lst = 1; /* Set end of ram entries */
}
#endif
static void inline video_mode_addentry (VRAM * vr,
int Hx, int Vx, int Fx, int Bx,
@ -501,7 +511,7 @@ static void inline video_mode_addentry (VRAM * vr,
vr->lst = LST;
}
#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i)
#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i)
static int video_mode_generate (void)
{
@ -539,9 +549,12 @@ static int video_mode_generate (void)
Y1 = video_panning_value_y & 0xfffe;
Y2 = DY - Y1;
debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n",
X1, X2, Y1, Y2, DX, DY, VIDEO_COLS);
#ifdef VIDEO_MODE_NTSC
/*
* Hx Vx Fx Bx VDS INT LCYC LP LST
* Hx Vx Fx Bx VDS INT LCYC LP LST
*
* Retrace blanking
*/
@ -641,6 +654,73 @@ static int video_mode_generate (void)
#endif
#ifdef VIDEO_MODE_PAL
#if defined(CONFIG_RRVISION)
#define HPW 160 /* horizontal pulse width (was 139) */
#define VPW 2 /* vertical pulse width */
#define HBP 104 /* horizontal back porch (was 112) */
#define VBP 19 /* vertical back porch (was 19) */
#define VID_R 240 /* number of rows */
debug ("[VIDEO CTRL] Starting to add controller entries...");
/*
* Even field
*/
ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
/*
* Active area
*/
ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
/*
* Odd field
*/
ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0);
ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
/*
* Active area
*/
ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
debug ("done\n");
#else /* !CONFIG_RRVISION */
/*
* Hx Vx Fx Bx VDS INT LCYC LP LST
*
@ -692,7 +772,9 @@ static int video_mode_generate (void)
* one more cycle loop and a last identifier)
*/
video_mode_dupefield (vr, &vr[entry], entry);
#endif
#endif /* CONFIG_RRVISION */
#endif /* VIDEO_MODE_PAL */
/* See what FIFO are we using */
fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS);
@ -829,26 +911,19 @@ static void video_ctrl_init (void *memptr)
debug ("[VIDEO CTRL] Turning on video port led...\n");
SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
#endif
#ifdef CONFIG_RRVISION
/* enable clock: set PD3 to VCLK, PC5 to HIGH */
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
debug ("PDPAR=%04X PDDIR=%04X PDDAT=%04X\n",
immr->im_ioport.iop_pdpar,
immr->im_ioport.iop_pddir,
immr->im_ioport.iop_pddat);
debug ("[RRvision] PC5 -> Output (1): ");
immr->im_ioport.iop_pcpar &= ~(0x0400);
immr->im_ioport.iop_pcdir |= 0x0400 ;
immr->im_ioport.iop_pcdat |= 0x0400 ;
debug ("PCPAR=%04X PCDIR=%04X PCDAT=%04X\n",
immr->im_ioport.iop_pcpar,
immr->im_ioport.iop_pcdir,
immr->im_ioport.iop_pcdat);
}
debug ("PC5->Output(1): enable PAL clock");
immap->im_ioport.iop_pcpar &= ~(0x0400);
immap->im_ioport.iop_pcdir |= 0x0400 ;
immap->im_ioport.iop_pcdat |= 0x0400 ;
debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
immap->im_ioport.iop_pdpar,
immap->im_ioport.iop_pddir,
immap->im_ioport.iop_pddat);
debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
immap->im_ioport.iop_pcpar,
immap->im_ioport.iop_pcdir,
immap->im_ioport.iop_pcdat);
#endif /* CONFIG_RRVISION */
/* Blanking the screen. */

6
doc/README.POST
View file

@ -212,7 +212,7 @@ struct post_test {
argument will be a pointer to the board info structure, while
the second will be a combination of bit flags specifying the
mode the test is running in (POST_POWERON, POST_NORMAL,
POST_POWERFAIL, POST_MANUAL) and whether the last execution of
POST_SLOWTEST, POST_MANUAL) and whether the last execution of
the test caused system rebooting (POST_REBOOT). The routine will
return 0 on successful execution of the test, and 1 if the test
failed.
@ -220,7 +220,7 @@ struct post_test {
The lists of the POST tests that should be run at power-on/normal/
power-fail booting will be kept in the environment. Namely, the
following environment variables will be used: post_poweron,
powet_normal, post_shutdown.
powet_normal, post_slowtest.
2.1.2. Test results
@ -253,7 +253,7 @@ composed of post_test structures:
"On-board peripherals test", "board", \
" This test performs full check-up of the " \
"on-board hardware.", \
POST_RAM | POST_POWERFAIL, \
POST_RAM | POST_SLOWTEST, \
&board_post_test \
}

2
doc/README.autoboot
View file

@ -141,7 +141,7 @@ What they do
Using the CONFIG_AUTOBOOT_DELAY_STR2 / bootdelaykey2 and/or
CONFIG_AUTOBOOT_STOP_STR2 / bootstopkey #defines and/or
environment variables you can specify a second, alternate
string (which allows you to haw two "password" strings).
string (which allows you to have two "password" strings).
CONFIG_ZERO_BOOTDELAY_CHECK

4
drivers/natsemi.c
View file

@ -306,8 +306,8 @@ natsemi_initialize(bd_t * bis)
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xF; /* Masked out the low bits that are addresses. */
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

2
dtt/ds1621.c
View file

@ -85,7 +85,7 @@ int dtt_write(int sensor, int reg, int val)
* Calculate sensor address and register.
*
*/
sensor = DTT_I2C_DEV_CODE + (sensor & sensor);
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
/*
* Handle various data sizes.

1
include/asm-ppc/global_data.h
View file

@ -73,6 +73,7 @@ typedef struct global_data {
#ifdef CONFIG_POST
unsigned long post_log_word; /* Record POST activities */
unsigned long post_init_f_time; /* When post_init_f started */
unsigned long post_hotkeys_latch; /* If the post hotkeys pressed */
#endif
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;

9
include/asm-ppc/processor.h
View file

@ -524,8 +524,15 @@
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
#define PVR_8260 PVR_8240
/*
* PowerQUICC II family processors report different PVR values depending
* on silicon process (HiP3, HiP4, HiP7, etc.)
*/
#define PVR_8260 PVR_8240
#define PVR_8260_HIP3 0x00810101
#define PVR_8260_HIP4 0x80811014
#define PVR_8260_HIP7 0x80822011
/* I am just adding a single entry for 8260 boards. I think we may be
* able to combine mbx, fads, rpxlite, bseip, and classic into a single

2
include/configs/A3000.h
View file

@ -114,6 +114,8 @@
#define PCI_ENET1_MEMADDR 0x81000000
#define PCI_ENET2_IOADDR 0x82000000
#define PCI_ENET2_MEMADDR 0x82000000
#define PCI_ENET3_IOADDR 0x83000000
#define PCI_ENET3_MEMADDR 0x83000000
/*-----------------------------------------------------------------------

8
include/configs/MPC8260ADS.h
View file

@ -206,6 +206,14 @@
#define CFG_FLASH_SIZE 8
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define CFG_JFFS2_FIRST_SECTOR 1
#define CFG_JFFS2_LAST_SECTOR 27
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
/* this is stuff came out of the Motorola docs */
#define CFG_DEFAULT_IMMR 0x0F010000

7
include/configs/RRvision.h
View file

@ -100,13 +100,13 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#if 1
#ifndef CONFIG_LCD
#define CONFIG_VIDEO 1 /* To enable the video initialization */
/* Video related */
#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x2A /* ALSB to ground */
#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
#endif
/* enable I2C and select the hardware/software driver */
@ -344,6 +344,7 @@
*-----------------------------------------------------------------------
*
*/
/*#define CFG_DER 0x2002000F*/
#define CFG_DER 0
/*

4
include/configs/lwmon.h
View file

@ -579,6 +579,6 @@
#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
#undef CONFIG_MODEM_SUPPORT_DEBUG
#define CONFIG_MODEM_KEY_MAGIC "3C+3F" /* hold down these keys to enable modem */
#define CONFIG_MODEM_KEY_MAGIC "3C+3F" /* press F3 + F6 keys to enable modem */
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
#endif /* __CONFIG_H */

1
include/image.h
View file

@ -63,6 +63,7 @@
#define IH_CPU_SH 9 /* SuperH */
#define IH_CPU_SPARC 10 /* Sparc */
#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
#define IH_CPU_M68K 12 /* M68K */
/*
* Image Types

15
include/mpc8260.h
View file

@ -300,14 +300,15 @@
/*-----------------------------------------------------------------------
* SCMR - System Clock Mode Register 9-9
*/
#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
#define SCMR_CORECNF_SHIFT 24
#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
#define SCMR_BUSDF_SHIFT 20
#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
#define SCMR_CPMDF_SHIFT 16
#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
#define SCMR_BUSDF_SHIFT 20
#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
#define SCMR_CPMDF_SHIFT 16
#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */
#define SCMR_PLLMF_SHIFT 0

11
include/post.h
View file

@ -30,8 +30,8 @@
#ifdef CONFIG_POST
#define POST_POWERON 0x01 /* test runs on power-on booting */
#define POST_POWERNORMAL 0x02 /* test runs on normal booting */
#define POST_POWERFAIL 0x04 /* test runs on power-fail booting */
#define POST_NORMAL 0x02 /* test runs on normal booting */
#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
#define POST_ROM 0x0100 /* test runs in ROM */
@ -41,9 +41,9 @@
#define POST_PREREL 0x1000 /* test runs before relocation */
#define POST_MEM (POST_RAM | POST_ROM)
#define POST_ALWAYS (POST_POWERNORMAL | \
POST_POWERFAIL | \
POST_MANUAL | \
#define POST_ALWAYS (POST_NORMAL | \
POST_SLOWTEST | \
POST_MANUAL | \
POST_POWERON )
#ifndef __ASSEMBLY__
@ -71,6 +71,7 @@ unsigned long post_time_ms (unsigned long base);
extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(gd_t *);
#endif /* __ASSEMBLY__ */

2
include/version.h
View file

@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
#define U_BOOT_VERSION "U-Boot 0.4.2"
#define U_BOOT_VERSION "U-Boot 0.4.3"
#endif /* __VERSION_H__ */

16
include/video_ad7176.h
View file

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -26,21 +26,21 @@
#define VIDEO_ENCODER_NAME "Analog Devices AD7176"
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
#undef VIDEO_MODE_RGB
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
#undef VIDEO_MODE_RGB
#define VIDEO_MODE_BPP 16
#ifdef VIDEO_MODE_PAL
#ifdef VIDEO_MODE_PAL
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 576
#define VIDEO_VISIBLE_COLS 640
#define VIDEO_VISIBLE_ROWS 480
#endif
#ifdef VIDEO_MODE_NTSC
#ifdef VIDEO_MODE_NTSC
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 525
#define VIDEO_VISIBLE_COLS 640
@ -54,7 +54,7 @@ static unsigned char video_encoder_data[] = {
0x82,
#else
0x02, /* Mode Register 1 */
#endif
#endif /* VIDEO_DEBUG_COLORBARS */
0x16, /* Subcarrier Freq 0 */
0x7c, /* Subcarrier Freq 1 */
0xf0, /* Subcarrier Freq 2 */
@ -81,7 +81,7 @@ static unsigned char video_encoder_data[] = {
0x82,
#else
0x02, /* Mode Register 1 (2) */
#endif
#endif /* VIDEO_DEBUG_COLORBARS */
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */

157
include/video_ad7177.h
View file

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -24,25 +24,25 @@
#ifndef _VIDEO_AD7177_H_
#define _VIDEO_AD7177_H_
/*#define VIDEO_DEBUG_DISABLE_COLORS 0 */
/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */
#define VIDEO_ENCODER_NAME "Analog Devices AD7177"
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
#undef VIDEO_MODE_RGB
#undef VIDEO_MODE_RGB
#define VIDEO_MODE_BPP 16
#ifdef VIDEO_MODE_PAL
#ifdef VIDEO_MODE_PAL
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 576
#define VIDEO_VISIBLE_COLS 640
#define VIDEO_VISIBLE_ROWS 480
#endif
#ifdef VIDEO_MODE_NTSC
#ifdef VIDEO_MODE_NTSC
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 525
#define VIDEO_VISIBLE_COLS 640
@ -52,97 +52,98 @@
static unsigned char
video_encoder_data[] = {
#ifdef VIDEO_MODE_NTSC
0x04, /* Mode Register 0 */
0x04, /* Mode Register 0 */
#ifdef VIDEO_DEBUG_COLORBARS
0xc2,
#else
0x42, /* Mode Register 1 */
#endif
0x16, /* Subcarrier Freq 0 */
0x7c, /* Subcarrier Freq 1 */
0xf0, /* Subcarrier Freq 2 */
0x21, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x08, /* Mode Register 2 */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08 /* Mode Register 3 */
0x42, /* Mode Register 1 */
#endif /* VIDEO_DEBUG_COLORBARS */
0x16, /* Subcarrier Freq 0 */
0x7c, /* Subcarrier Freq 1 */
0xf0, /* Subcarrier Freq 2 */
0x21, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x08, /* Mode Register 2 */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08, /* Mode Register 3 */
#endif /* VIDEO_MODE_NTSC */
#endif
#ifdef VIDEO_MODE_PAL
#ifdef VIDEO_MODE_RGB_OUT
0x69, /* Mode Register 0 */
0x69, /* Mode Register 0 */
#ifdef VIDEO_DEBUG_COLORBARS
0xc0, /* Mode Register 1 (c0) */
0xc0, /* Mode Register 1 (c0) */
#else
0x40, /* Mode Register 1 (c0) */
#endif
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */
0x2a, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x28, /* Mode Register 2 */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08 /* Mode Register 3 */
0x40, /* Mode Register 1 (c0) */
#endif /* VIDEO_DEBUG_COLORBARS */
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */
0x2a, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x28, /* Mode Register 2 */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08, /* Mode Register 3 */
#else
#else /* ! VIDEO_MODE_RGB_OUT */
0x09, /* Mode Register 0 (was 01) */
#ifdef VIDEO_DEBUG_COLORBARS
0xd8, /* */
0xd8, /* */
#else
0x59, /* Mode Register 1 (was 58) */
#endif
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */
0x2a, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
#endif /* VIDEO_DEBUG_COLORBARS */
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */
0x2a, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 (was a) */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
#ifdef VIDEO_DEBUG_LOWPOWER
#ifdef VIDEO_DEBUG_DISABLE_COLORS
0x98, /* Mode Register 2 */
#else
0x88, /* Mode Register 2 */
#endif
0x98, /* Mode Register 2 */
#else
0x88, /* Mode Register 2 */
#endif /* VIDEO_DEBUG_DISABLE_COLORS */
#else /* ! VIDEO_DEBUG_LOWPOWER */
#ifdef VIDEO_DEBUG_DISABLE_COLORS
0x18, /* Mode Register 2 */
0x18, /* Mode Register 2 */
#else
0x08, /* Mode Register 2 */
#endif
#endif
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08 /* Mode Register 3 */
#endif
#endif
0x08, /* Mode Register 2 */
#endif /* VIDEO_DEBUG_DISABLE_COLORS */
#endif /* VIDEO_DEBUG_LOWPOWER */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x08 /* Mode Register 3 */
#endif /* VIDEO_MODE_RGB_OUT */
#endif /* VIDEO_MODE_PAL */
} ;
#endif
#endif /* _VIDEO_AD7177_H_ */

36
include/video_ad7179.h Normal file
View file

@ -0,0 +1,36 @@
/*
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_AD7179_H_
#define _VIDEO_AD7179_H_
/*
* The video encoder data are board specific now!
*/
#if defined(CONFIG_RRVISION)
#include "../board/RRvision/video_ad7179.h"
#else
#error "Please provide a board-specific video_ad7179.h"
#endif
#endif /* _VIDEO_AD7179_H_ */

2
lib_i386/board.c
View file

@ -418,7 +418,7 @@ void start_i386boot (void)
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
if (post_bootmode_get(0) & POST_POWERFAIL) {
if (post_bootmode_get(0) & POST_SLOWTEST) {
post_bootmode_clear();
board_poweroff();
}

12
lib_ppc/board.c
View file

@ -526,7 +526,10 @@ void board_init_f (ulong bootflag)
#ifdef CONFIG_POST
post_bootmode_init();
post_run (NULL, POST_ROM | post_bootmode_get(0));
if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
post_run (NULL, POST_ROM | POST_SLOWTEST);
else
post_run (NULL, POST_ROM | post_bootmode_get(0));
#endif
WATCHDOG_RESET();
@ -897,8 +900,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
#endif
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
if (post_bootmode_get(0) & POST_POWERFAIL) {
if (gd->post_hotkeys_latch)
post_run (NULL, POST_RAM | POST_SLOWTEST);
else
post_run (NULL, POST_RAM | post_bootmode_get(0));
if (post_bootmode_get(0) & POST_SLOWTEST) {
post_bootmode_clear();
board_poweroff();
}

6
post/memory.c
View file

@ -146,7 +146,7 @@
* regions of RAM around each 1Mb boundary. For example, for 64Mb
* RAM the following areas are verified: 0x00000000-0x00000800,
* 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
* 0x04000000. If the test is run in power-fail mode, it verifies
* 0x04000000. If the test is run in slow-test mode, it verifies
* the whole RAM.
*/
@ -460,9 +460,9 @@ int memory_post_test (int flags)
256 << 20 : bd->bi_memsize) - (1 << 20);
if (flags & POST_POWERFAIL) {
if (flags & POST_SLOWTEST) {
ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
} else { /* POST_POWERNORMAL */
} else { /* POST_NORMAL */
unsigned long i;

6
post/post.c
View file

@ -68,7 +68,7 @@ void post_bootmode_init (void)
if (bootmode == 0) {
bootmode = POST_POWERON;
} else if (bootmode == POST_POWERON) {
bootmode = POST_POWERNORMAL;
bootmode = POST_NORMAL;
} else {
return;
}
@ -153,8 +153,8 @@ static void post_bootmode_test_off (void)
static void post_get_flags (int *test_flags)
{
int flag[] = { POST_POWERON, POST_POWERNORMAL, POST_POWERFAIL };
char *var[] = { "post_poweron", "post_normal", "post_shutdown" };
int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
int varnum = sizeof (var) / sizeof (var[0]);
char list[128]; /* long enough for POST list */
char *name;

54
post/sysmon.c
View file

@ -98,6 +98,7 @@ struct sysmon_table_s
void (*exec_before)(sysmon_table_t *);
void (*exec_after)(sysmon_table_t *);
int unit_precision;
int unit_div;
int unit_min;
int unit_max;
@ -105,31 +106,34 @@ struct sysmon_table_s
uint val_min;
uint val_max;
int val_valid;
uint val_min_alt;
uint val_max_alt;
int val_valid_alt;
uint addr;
};
static sysmon_table_t sysmon_table[] =
{
{"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable,
1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x27},
1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x67, 0xC6, 0, 0x27},
{"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable,
100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0x29},
1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xAE, 0xF1, 0, 0x29},
{"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL,
1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0x22},
100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22},
{"+5V logic", "V", &sysmon_lm87, NULL, NULL,
1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0x23},
{"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL,
100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23},
{"+12V PCMCIA", "V", &sysmon_lm87, NULL, NULL,
1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0x21},
{"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL,
100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21},
{"+12V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable,
1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0x24},
{"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable,
100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24},
{"+5V standby", "V", &sysmon_pic, NULL, NULL,
1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0x7C},
{"+ 5 V standby", "V", &sysmon_pic, NULL, NULL,
100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C},
};
static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
@ -176,31 +180,38 @@ void sysmon_reloc (void)
}
}
static char * sysmon_unit_value (sysmon_table_t * s, uint val)
static char *sysmon_unit_value (sysmon_table_t *s, uint val)
{
static char buf[32];
int unit_val =
s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
char * p;
char *p, sign;
int dec, frac;
sprintf(buf, "%+d", unit_val / s->unit_div);
if (unit_val < 0) {
sign = '-';
unit_val = -unit_val;
} else {
sign = '+';
}
frac = (unit_val > 0 ? unit_val : -unit_val) % s->unit_div;
p = buf + strlen(buf);
p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
dec = s->unit_div;
frac = unit_val % s->unit_div;
frac /= (s->unit_div / s->unit_precision);
dec = s->unit_precision;
if (dec != 1)
{
*p++ = '.';
}
for (dec /= 10; dec != 0; dec /= 10)
{
*p++ = '0' + frac / dec % 10;
*p++ = '0' + (frac / dec) % 10;
}
strcpy(p, s->unit_name);
return buf;
@ -256,7 +267,7 @@ static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr)
static void sysmon_ccfl_disable (sysmon_table_t * this)
{
if (!this->val_valid)
if (!this->val_valid_alt)
{
sysmon_temp_invalid = 1;
}
@ -300,6 +311,7 @@ int sysmon_post_test (int flags)
val = t->sysmon->read(t->sysmon, t->addr);
t->val_valid = val >= t->val_min && val <= t->val_max;
t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
if (t->exec_after)
{

8
post/tests.c
View file

@ -68,7 +68,7 @@ struct post_test post_list[] =
"Watchdog timer test",
"watchdog",
"This test checks the watchdog timer.",
POST_RAM | POST_POWERON | POST_POWERFAIL | POST_MANUAL | POST_REBOOT,
POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
&watchdog_post_test,
NULL,
NULL,
@ -92,7 +92,7 @@ struct post_test post_list[] =
"RTC test",
"rtc",
"This test verifies the RTC operation.",
POST_RAM | POST_POWERFAIL | POST_MANUAL,
POST_RAM | POST_SLOWTEST | POST_MANUAL,
&rtc_post_test,
NULL,
NULL,
@ -104,7 +104,7 @@ struct post_test post_list[] =
"Memory test",
"memory",
"This test checks RAM.",
POST_ROM | POST_POWERON | POST_POWERFAIL | POST_PREREL,
POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
&memory_post_test,
NULL,
NULL,
@ -129,7 +129,7 @@ struct post_test post_list[] =
"UART test",
"uart",
"This test verifies the UART operation.",
POST_RAM | POST_POWERFAIL | POST_MANUAL,
POST_RAM | POST_SLOWTEST | POST_MANUAL,
&uart_post_test,
NULL,
NULL,

1
tools/mkimage.c
View file

@ -70,6 +70,7 @@ table_entry_t arch_name[] = {
{ IH_CPU_SH, "sh", "SuperH", },
{ IH_CPU_SPARC, "sparc", "SPARC", },
{ IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
{ IH_CPU_M68K, "m68k", "MC68000", },
{ -1, "", "", },
};