mirror of
https://github.com/AsahiLinux/u-boot
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cb056005dc
Aardvark does not have a real PCIe Root Port device on the root bus. Instead it has PCIe registers of PCIe Root Port device mapped in internal Aardvark memory space starting at offset 0xc0. The PCIe Root Port itself is normally available as a PCI Bridge device on the root bus with bus number zero. Aardvark instead has the configuration registers of this PCI Bridge at offset 0x00 of Aardvark's memory space, but the class code of this device is Mass Storage Controller (0x010400), instead of PCI Bridge (0x600400), which causes U-Boot to fail to recognize it as a P2P Bridge Add a hook into the pcie_advk_read_config() / pcie_advk_write_config() functions to redirect access for root bus from PIO transfer to this internal Aardvark memory space. This will allow U-Boot to access configuration space of this PCI Bridge which represents PCIe Root Port. Redirect access to PCI Bridge registers in range 0x10 - 0x34 to driver's internal buffer (cfgcache[]). This is because at those addresses Aardvark has different registers, incompatible with config space of a PCI Bridge. Redirect access to PCI Bridge register PCI_ROM_ADDRESS1 (0x38) to Aardvark internal address for that register (0x30). When reading PCI Bridge register PCI_HEADER_TYPE, set it explicitly to value Type 1 (PCI_HEADER_TYPE_BRIDGE) as PCI Bridge must be of Type 1. When writing to PCI_PRIMARY_BUS or PCI_SECONDARY_BUS registers on this PCI Bridge, correctly update driver's first_busno and sec_busno variables, so that pcie_advk_addr_valid() function can check if address of any device behind the root bus is valid and that PIO transfers are started with correct config type (1 vs 0), which is required for accessing devices behind some PCI bridge after the root bus. U-Boot's PCI_PNP code sets primary and secondary bus numbers as relative to the configured bus number of the root bus. This is done so that U-Boot can support multiple PCIe host bridges or multiple root port buses, when internal bus numbers are different. Now that root bus is available, update code in pcie_advk_read_config() and pcie_advk_write_config() functions to correctly calculate real Aardvark bus number of the target device from U-Boot's bus number as: busno = PCI_BUS(bdf) - dev_seq(bus) Stefan: Small fix of header masking as suggested by Pali. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
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| .. | ||
| adc | ||
| ata | ||
| axi | ||
| bios_emulator | ||
| block | ||
| bootcount | ||
| bus | ||
| button | ||
| cache | ||
| clk | ||
| core | ||
| cpu | ||
| crypto | ||
| ddr | ||
| demo | ||
| dfu | ||
| dma | ||
| fastboot | ||
| firmware | ||
| fpga | ||
| gpio | ||
| hwspinlock | ||
| i2c | ||
| input | ||
| led | ||
| mailbox | ||
| memory | ||
| misc | ||
| mmc | ||
| mtd | ||
| mux | ||
| net | ||
| nvme | ||
| pch | ||
| pci | ||
| pci_endpoint | ||
| phy | ||
| pinctrl | ||
| power | ||
| pwm | ||
| qe | ||
| ram | ||
| reboot-mode | ||
| remoteproc | ||
| reset | ||
| rng | ||
| rtc | ||
| scsi | ||
| serial | ||
| smem | ||
| soc | ||
| sound | ||
| spi | ||
| spmi | ||
| sysinfo | ||
| sysreset | ||
| tee | ||
| thermal | ||
| timer | ||
| tpm | ||
| ufs | ||
| usb | ||
| video | ||
| virtio | ||
| w1 | ||
| w1-eeprom | ||
| watchdog | ||
| xen | ||
| Kconfig | ||
| Makefile | ||