mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-24 16:32:20 +00:00
ca8a329a1b
This converts the following to Kconfig: CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE CONFIG_TPL_PAD_TO CONFIG_TPL_MAX_SIZE Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the existing places. Signed-off-by: Tom Rini <trini@konsulko.com>
78 lines
2 KiB
C
78 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __IMX8M_CM_H
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#define __IMX8M_CM_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x187FF0
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#define CONFIG_SPL_BSS_START_ADDR 0x00180000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x182000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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/* ENET Config */
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/* ENET1 */
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"scriptaddr=0x43500000\0" \
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"kernel_addr_r=0x40880000\0" \
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"image=Image\0" \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x43000000\0" \
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"boot_fdt=try\0" \
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"fdt_file=imx8mq-cm.dtb\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
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#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#endif
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