mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 06:12:58 +00:00
4e99899bd5
The "notable" disappearances are: - the pac193x stanza - there's nothing in mainline linux w.r.t. bindings for this & what is going to appear in mainline linux is going to be incompatible with what is currently in U-Boot. - operating points - these operating points should not be set at the soc.dtsi level as they may not be possible depending on the design programmed to the FPGA - clock output names - there are defines for the clock indices, these should not be needed - the dt maintainers in linux NAKed using defines for IRQ numbers - the qspi nand, which is not part of the icicle's default configuration is removed. Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
511 lines
12 KiB
Text
511 lines
12 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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#include "dt-bindings/clock/microchip-mpfs-clock.h"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PolarFire SoC";
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compatible = "microchip,mpfs";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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clocks = <&clkcfg CLK_CPU>;
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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next-level-cache = <&cctrllr>;
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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next-level-cache = <&cctrllr>;
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status = "okay";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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next-level-cache = <&cctrllr>;
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status = "okay";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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next-level-cache = <&cctrllr>;
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status = "okay";
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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};
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};
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};
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refclk: mssrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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syscontroller: syscontroller {
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compatible = "microchip,mpfs-sys-controller";
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mboxes = <&mbox 0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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cctrllr: cache-controller@2010000 {
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compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
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reg = <0x0 0x2010000 0x0 0x1000>;
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1>, <3>, <4>, <2>;
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};
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clint: clint@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0xC000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>,
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<&cpu4_intc 3>, <&cpu4_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>,
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<&cpu4_intc 11>, <&cpu4_intc 9>;
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riscv,ndev = <186>;
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};
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pdma: dma-controller@3000000 {
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compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
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dma-channels = <4>;
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#dma-cells = <1>;
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&refclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ccc_se: clock-controller@38010000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
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<0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_ne: clock-controller@38040000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
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<0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_nw: clock-controller@38100000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
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<0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_sw: clock-controller@38400000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
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<0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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mmuart0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <90>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART0>;
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status = "disabled"; /* Reserved for the HSS */
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};
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mmuart1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <91>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART1>;
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status = "disabled";
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};
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mmuart2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <92>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART2>;
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status = "disabled";
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};
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mmuart3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <93>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART3>;
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status = "disabled";
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};
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mmuart4: serial@20106000 {
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compatible = "ns16550a";
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reg = <0x0 0x20106000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <94>;
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clocks = <&clkcfg CLK_MMUART4>;
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current-speed = <115200>;
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status = "disabled";
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};
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/* Common node entry for emmc/sd */
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mmc: mmc@20008000 {
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compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88>;
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clocks = <&clkcfg CLK_MMC>;
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max-frequency = <200000000>;
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status = "disabled";
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};
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spi0: spi@20108000 {
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compatible = "microchip,mpfs-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20108000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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clocks = <&clkcfg CLK_SPI0>;
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status = "disabled";
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};
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spi1: spi@20109000 {
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compatible = "microchip,mpfs-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20109000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <55>;
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clocks = <&clkcfg CLK_SPI1>;
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status = "disabled";
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};
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qspi: spi@21000000 {
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compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21000000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <85>;
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clocks = <&clkcfg CLK_QSPI>;
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status = "disabled";
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};
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i2c0: i2c@2010a000 {
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compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
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reg = <0x0 0x2010a000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <58>;
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clocks = <&clkcfg CLK_I2C0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@2010b000 {
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compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
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reg = <0x0 0x2010b000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <61>;
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clocks = <&clkcfg CLK_I2C1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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can0: can@2010c000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010c000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN0>;
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interrupt-parent = <&plic>;
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interrupts = <56>;
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status = "disabled";
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};
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can1: can@2010d000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010d000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN1>;
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interrupt-parent = <&plic>;
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interrupts = <57>;
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status = "disabled";
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};
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mac0: ethernet@20110000 {
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC0>;
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status = "disabled";
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};
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mac1: ethernet@20112000 {
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC1>;
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status = "disabled";
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};
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gpio0: gpio@20120000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x0 0x20120000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@20121000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x0 0x20121000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio@20122000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x0 0x20122000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO2>;
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|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@20124000 {
|
|
compatible = "microchip,mpfs-rtc";
|
|
reg = <0x0 0x20124000 0x0 0x1000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <80>, <81>;
|
|
clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
|
|
clock-names = "rtc", "rtcref";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb: usb@20201000 {
|
|
compatible = "microchip,mpfs-musb";
|
|
reg = <0x0 0x20201000 0x0 0x1000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <86>, <87>;
|
|
clocks = <&clkcfg CLK_USB>;
|
|
interrupt-names = "dma","mc";
|
|
status = "disabled";
|
|
};
|
|
|
|
mbox: mailbox@37020000 {
|
|
compatible = "microchip,mpfs-mailbox";
|
|
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
|
|
<0x0 0x37020800 0x0 0x100>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <96>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|