mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
835 lines
21 KiB
C
835 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2003
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* Ingo Assmus <ingo.assmus@keymile.com>
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*
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* based on - Driver for MV64360X ethernet ports
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* Copyright (C) 2002 rabeeh@galileo.co.il
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <net.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <wait_bit.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/types.h>
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#include <asm/system.h>
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#include <asm/byteorder.h>
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#include <asm/arch/cpu.h>
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#if defined(CONFIG_ARCH_KIRKWOOD)
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#include <asm/arch/soc.h>
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#elif defined(CONFIG_ARCH_ORION5X)
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#include <asm/arch/orion5x.h>
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#endif
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#include "mvgbe.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define MV_PHY_ADR_REQUEST 0xee
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#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
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#define MVGBE_PGADR_REG 22
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#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int smi_wait_ready(struct mvgbe_device *dmvgbe)
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{
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int ret;
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ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false,
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MVGBE_PHY_SMI_TIMEOUT_MS, false);
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if (ret) {
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printf("Error: SMI busy timeout\n");
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return ret;
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}
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return 0;
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}
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static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
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int devad, int reg_ofs)
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{
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struct mvgbe_registers *regs = dmvgbe->regs;
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u32 smi_reg;
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u32 timeout;
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u16 data = 0;
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/* Phyadr read request */
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if (phy_adr == MV_PHY_ADR_REQUEST &&
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reg_ofs == MV_PHY_ADR_REQUEST) {
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/* */
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data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
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return data;
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}
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/* check parameters */
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if (phy_adr > PHYADR_MASK) {
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printf("Err..(%s) Invalid PHY address %d\n",
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__func__, phy_adr);
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return -EFAULT;
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}
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if (reg_ofs > PHYREG_MASK) {
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printf("Err..(%s) Invalid register offset %d\n",
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__func__, reg_ofs);
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return -EFAULT;
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}
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/* wait till the SMI is not busy */
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if (smi_wait_ready(dmvgbe) < 0)
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return -EFAULT;
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/* fill the phy address and regiser offset and read opcode */
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smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
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| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
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| MVGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
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/*wait till read value is ready */
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timeout = MVGBE_PHY_SMI_TIMEOUT;
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do {
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/* read smi register */
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smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI read ready timeout\n",
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__func__);
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return -EFAULT;
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}
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} while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
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/* Wait for the data to update in the SMI register */
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for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
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;
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data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
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debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs,
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data);
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return data;
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}
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/*
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* smi_reg_read - miiphy_read callback function.
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*
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* Returns 16bit phy register value, or -EFAULT on error
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*/
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static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
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int reg_ofs)
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{
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struct mvgbe_device *dmvgbe = bus->priv;
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return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
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}
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static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
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int devad, int reg_ofs, u16 data)
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{
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struct mvgbe_registers *regs = dmvgbe->regs;
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u32 smi_reg;
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/* Phyadr write request*/
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if (phy_adr == MV_PHY_ADR_REQUEST &&
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reg_ofs == MV_PHY_ADR_REQUEST) {
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MVGBE_REG_WR(regs->phyadr, data);
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return 0;
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}
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/* check parameters */
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if (phy_adr > PHYADR_MASK) {
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printf("Err..(%s) Invalid phy address\n", __func__);
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return -EINVAL;
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}
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if (reg_ofs > PHYREG_MASK) {
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printf("Err..(%s) Invalid register offset\n", __func__);
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return -EFAULT;
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}
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/* wait till the SMI is not busy */
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if (smi_wait_ready(dmvgbe) < 0)
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return -EFAULT;
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/* fill the phy addr and reg offset and write opcode and data */
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smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
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smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
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| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
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smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
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return 0;
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}
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/*
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* smi_reg_write - miiphy_write callback function.
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*
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* Returns 0 if write succeed, -EFAULT on error
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*/
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static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
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int reg_ofs, u16 data)
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{
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struct mvgbe_device *dmvgbe = bus->priv;
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return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
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}
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#endif
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/* Stop and checks all queues */
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static void stop_queue(u32 * qreg)
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{
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u32 reg_data;
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reg_data = readl(qreg);
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if (reg_data & 0xFF) {
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/* Issue stop command for active channels only */
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writel((reg_data << 8), qreg);
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/* Wait for all queue activity to terminate. */
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do {
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/*
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* Check port cause register that all queues
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* are stopped
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*/
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reg_data = readl(qreg);
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}
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while (reg_data & 0xFF);
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}
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}
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/*
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* set_access_control - Config address decode parameters for Ethernet unit
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*
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* This function configures the address decode parameters for the Gigabit
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* Ethernet Controller according the given parameters struct.
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*
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* @regs Register struct pointer.
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* @param Address decode parameter struct.
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*/
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static void set_access_control(struct mvgbe_registers *regs,
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struct mvgbe_winparam *param)
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{
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u32 access_prot_reg;
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/* Set access control register */
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access_prot_reg = MVGBE_REG_RD(regs->epap);
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/* clear window permission */
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access_prot_reg &= (~(3 << (param->win * 2)));
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access_prot_reg |= (param->access_ctrl << (param->win * 2));
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MVGBE_REG_WR(regs->epap, access_prot_reg);
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/* Set window Size reg (SR) */
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MVGBE_REG_WR(regs->barsz[param->win].size,
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(((param->size / 0x10000) - 1) << 16));
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/* Set window Base address reg (BA) */
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MVGBE_REG_WR(regs->barsz[param->win].bar,
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(param->target | param->attrib | param->base_addr));
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/* High address remap reg (HARR) */
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if (param->win < 4)
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MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
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/* Base address enable reg (BARER) */
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if (param->enable == 1)
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MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
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else
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MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
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}
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static void set_dram_access(struct mvgbe_registers *regs)
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{
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struct mvgbe_winparam win_param;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Set access parameters for DRAM bank i */
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win_param.win = i; /* Use Ethernet window i */
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/* Window target - DDR */
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win_param.target = MVGBE_TARGET_DRAM;
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/* Enable full access */
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win_param.access_ctrl = EWIN_ACCESS_FULL;
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win_param.high_addr = 0;
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/* Get bank base and size */
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win_param.base_addr = gd->bd->bi_dram[i].start;
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win_param.size = gd->bd->bi_dram[i].size;
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if (win_param.size == 0)
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win_param.enable = 0;
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else
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win_param.enable = 1; /* Enable the access */
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/* Enable DRAM bank */
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switch (i) {
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case 0:
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win_param.attrib = EBAR_DRAM_CS0;
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break;
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case 1:
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win_param.attrib = EBAR_DRAM_CS1;
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break;
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case 2:
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win_param.attrib = EBAR_DRAM_CS2;
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break;
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case 3:
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win_param.attrib = EBAR_DRAM_CS3;
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break;
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default:
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/* invalid bank, disable access */
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win_param.enable = 0;
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win_param.attrib = 0;
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break;
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}
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/* Set the access control for address window(EPAPR) RD/WR */
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set_access_control(regs, &win_param);
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}
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}
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/*
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* port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
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*
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* Go through all the DA filter tables (Unicast, Special Multicast & Other
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* Multicast) and set each entry to 0.
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*/
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static void port_init_mac_tables(struct mvgbe_registers *regs)
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{
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int table_index;
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/* Clear DA filter unicast table (Ex_dFUT) */
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for (table_index = 0; table_index < 4; ++table_index)
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MVGBE_REG_WR(regs->dfut[table_index], 0);
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for (table_index = 0; table_index < 64; ++table_index) {
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/* Clear DA filter special multicast table (Ex_dFSMT) */
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MVGBE_REG_WR(regs->dfsmt[table_index], 0);
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/* Clear DA filter other multicast table (Ex_dFOMT) */
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MVGBE_REG_WR(regs->dfomt[table_index], 0);
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}
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}
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/*
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* port_uc_addr - This function Set the port unicast address table
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*
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* This function locates the proper entry in the Unicast table for the
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* specified MAC nibble and sets its properties according to function
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* parameters.
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* This function add/removes MAC addresses from the port unicast address
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* table.
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*
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* @uc_nibble Unicast MAC Address last nibble.
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* @option 0 = Add, 1 = remove address.
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*
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* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
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*/
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static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
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int option)
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{
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u32 unicast_reg;
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u32 tbl_offset;
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u32 reg_offset;
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/* Locate the Unicast table entry */
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uc_nibble = (0xf & uc_nibble);
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/* Register offset from unicast table base */
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tbl_offset = (uc_nibble / 4);
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/* Entry offset within the above register */
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reg_offset = uc_nibble % 4;
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switch (option) {
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case REJECT_MAC_ADDR:
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/*
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* Clear accepts frame bit at specified unicast
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* DA table entry
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*/
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unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
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unicast_reg &= (0xFF << (8 * reg_offset));
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MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
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break;
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case ACCEPT_MAC_ADDR:
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/* Set accepts frame bit at unicast DA filter table entry */
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unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
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unicast_reg &= (0xFF << (8 * reg_offset));
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unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
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MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
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break;
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default:
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return 0;
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}
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return 1;
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}
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/*
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* port_uc_addr_set - This function Set the port Unicast address.
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*/
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static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
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{
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struct mvgbe_registers *regs = dmvgbe->regs;
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u32 mac_h;
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u32 mac_l;
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mac_l = (p_addr[4] << 8) | (p_addr[5]);
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mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
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(p_addr[3] << 0);
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MVGBE_REG_WR(regs->macal, mac_l);
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MVGBE_REG_WR(regs->macah, mac_h);
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/* Accept frames of this address */
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port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
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}
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/*
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* mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
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*/
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static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
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{
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struct mvgbe_rxdesc *p_rx_desc;
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int i;
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/* initialize the Rx descriptors ring */
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p_rx_desc = dmvgbe->p_rxdesc;
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for (i = 0; i < RINGSZ; i++) {
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p_rx_desc->cmd_sts =
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MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
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p_rx_desc->buf_size = PKTSIZE_ALIGN;
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p_rx_desc->byte_cnt = 0;
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p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
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if (i == (RINGSZ - 1))
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p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
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else {
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p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
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((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
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p_rx_desc = p_rx_desc->nxtdesc_p;
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}
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}
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dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
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}
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static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
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const char *name)
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{
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struct mvgbe_registers *regs = dmvgbe->regs;
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/* setup RX rings */
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mvgbe_init_rx_desc_ring(dmvgbe);
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/* Clear the ethernet port interrupts */
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MVGBE_REG_WR(regs->ic, 0);
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MVGBE_REG_WR(regs->ice, 0);
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/* Unmask RX buffer and TX end interrupt */
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MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
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/* Unmask phy and link status changes interrupts */
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MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
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set_dram_access(regs);
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port_init_mac_tables(regs);
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port_uc_addr_set(dmvgbe, enetaddr);
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/* Assign port configuration and command. */
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MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
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MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
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MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
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/* Assign port SDMA configuration */
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MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
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MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
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MVGBE_REG_WR(regs->tqx[0].tqxtbc,
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(QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
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/* Turn off the port/RXUQ bandwidth limitation */
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MVGBE_REG_WR(regs->pmtu, 0);
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/* Set maximum receive buffer to 9700 bytes */
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MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
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| (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
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/* Enable port initially */
|
|
MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
|
|
|
|
/*
|
|
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
|
|
* disable the leaky bucket mechanism .
|
|
*/
|
|
MVGBE_REG_WR(regs->pmtu, 0);
|
|
|
|
/* Assignment of Rx CRDB of given RXUQ */
|
|
MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
|
|
/* ensure previous write is done before enabling Rx DMA */
|
|
isb();
|
|
/* Enable port Rx. */
|
|
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
|
|
{
|
|
struct mvgbe_registers *regs = dmvgbe->regs;
|
|
|
|
/* Disable all gigE address decoder */
|
|
MVGBE_REG_WR(regs->bare, 0x3f);
|
|
|
|
stop_queue(®s->tqc);
|
|
stop_queue(®s->rqc);
|
|
|
|
/* Disable port */
|
|
MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
|
|
/* Set port is not reset */
|
|
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
|
|
#ifdef CONFIG_SYS_MII_MODE
|
|
/* Set MMI interface up */
|
|
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
|
|
#endif
|
|
/* Disable & mask ethernet port interrupts */
|
|
MVGBE_REG_WR(regs->ic, 0);
|
|
MVGBE_REG_WR(regs->ice, 0);
|
|
MVGBE_REG_WR(regs->pim, 0);
|
|
MVGBE_REG_WR(regs->peim, 0);
|
|
}
|
|
|
|
static int mvgbe_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
|
|
int datasize)
|
|
{
|
|
struct mvgbe_registers *regs = dmvgbe->regs;
|
|
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
|
|
void *p = (void *)dataptr;
|
|
u32 cmd_sts;
|
|
u32 txuq0_reg_addr;
|
|
|
|
/* Copy buffer if it's misaligned */
|
|
if ((u32) dataptr & 0x07) {
|
|
if (datasize > PKTSIZE_ALIGN) {
|
|
printf("Non-aligned data too large (%d)\n",
|
|
datasize);
|
|
return -1;
|
|
}
|
|
|
|
memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
|
|
p = dmvgbe->p_aligned_txbuf;
|
|
}
|
|
|
|
p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
|
|
p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
|
|
p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
|
|
p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
|
|
p_txdesc->buf_ptr = (u8 *) p;
|
|
p_txdesc->byte_cnt = datasize;
|
|
|
|
/* Set this tc desc as zeroth TXUQ */
|
|
txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
|
|
writel((u32) p_txdesc, txuq0_reg_addr);
|
|
|
|
/* ensure tx desc writes above are performed before we start Tx DMA */
|
|
isb();
|
|
|
|
/* Apply send command using zeroth TXUQ */
|
|
MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
|
|
|
|
/*
|
|
* wait for packet xmit completion
|
|
*/
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
|
|
/* return fail if error is detected */
|
|
if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
|
|
(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
|
|
cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
|
|
printf("Err..(%s) in xmit packet\n", __func__);
|
|
return -1;
|
|
}
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
};
|
|
return 0;
|
|
}
|
|
|
|
static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
|
|
{
|
|
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
|
|
u32 cmd_sts;
|
|
u32 timeout = 0;
|
|
u32 rxdesc_curr_addr;
|
|
unsigned char *data;
|
|
int rx_bytes = 0;
|
|
|
|
*packetp = NULL;
|
|
|
|
/* wait untill rx packet available or timeout */
|
|
do {
|
|
if (timeout < MVGBE_PHY_SMI_TIMEOUT)
|
|
timeout++;
|
|
else {
|
|
debug("%s time out...\n", __func__);
|
|
return -1;
|
|
}
|
|
} while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
|
|
|
|
if (p_rxdesc_curr->byte_cnt != 0) {
|
|
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
|
|
__func__, (u32) p_rxdesc_curr->byte_cnt,
|
|
(u32) p_rxdesc_curr->buf_ptr,
|
|
(u32) p_rxdesc_curr->cmd_sts);
|
|
}
|
|
|
|
/*
|
|
* In case received a packet without first/last bits on
|
|
* OR the error summary bit is on,
|
|
* the packets needs to be dropeed.
|
|
*/
|
|
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
|
|
|
|
if ((cmd_sts &
|
|
(MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
|
|
!= (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
|
|
|
|
printf("Err..(%s) Dropping packet spread on"
|
|
" multiple descriptors\n", __func__);
|
|
|
|
} else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
|
|
|
|
printf("Err..(%s) Dropping packet with errors\n",
|
|
__func__);
|
|
|
|
} else {
|
|
/* !!! call higher layer processing */
|
|
debug("%s: Sending Received packet to"
|
|
" upper layer (net_process_received_packet)\n",
|
|
__func__);
|
|
|
|
data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
|
|
rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
|
|
RX_BUF_OFFSET);
|
|
|
|
*packetp = data;
|
|
}
|
|
/*
|
|
* free these descriptors and point next in the ring
|
|
*/
|
|
p_rxdesc_curr->cmd_sts =
|
|
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
|
|
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
|
|
p_rxdesc_curr->byte_cnt = 0;
|
|
|
|
rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
|
|
writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
|
|
|
|
return rx_bytes;
|
|
}
|
|
|
|
#if defined(CONFIG_PHYLIB)
|
|
static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
|
|
struct mii_dev *bus,
|
|
phy_interface_t phy_interface,
|
|
int phyid)
|
|
{
|
|
struct phy_device *phydev;
|
|
|
|
/* Set phy address of the port */
|
|
miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
|
|
phyid);
|
|
|
|
/* Make sure the selected PHY page is 0 before connecting */
|
|
miiphy_write(dev->name, phyid, MVGBE_PGADR_REG, 0);
|
|
|
|
phydev = phy_connect(bus, phyid, dev, phy_interface);
|
|
if (!phydev) {
|
|
printf("phy_connect failed\n");
|
|
return NULL;
|
|
}
|
|
|
|
phy_config(phydev);
|
|
phy_startup(phydev);
|
|
|
|
return phydev;
|
|
}
|
|
#endif /* CONFIG_PHYLIB */
|
|
|
|
static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
|
|
{
|
|
dmvgbe->p_rxdesc = memalign(PKTALIGN,
|
|
MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
|
|
if (!dmvgbe->p_rxdesc)
|
|
goto error1;
|
|
|
|
dmvgbe->p_rxbuf = memalign(PKTALIGN,
|
|
RINGSZ * PKTSIZE_ALIGN + 1);
|
|
if (!dmvgbe->p_rxbuf)
|
|
goto error2;
|
|
|
|
dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
|
|
if (!dmvgbe->p_aligned_txbuf)
|
|
goto error3;
|
|
|
|
dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
|
|
if (!dmvgbe->p_txdesc)
|
|
goto error4;
|
|
|
|
return 0;
|
|
|
|
error4:
|
|
free(dmvgbe->p_aligned_txbuf);
|
|
error3:
|
|
free(dmvgbe->p_rxbuf);
|
|
error2:
|
|
free(dmvgbe->p_rxdesc);
|
|
error1:
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
|
|
{
|
|
return dmvgbe->phyaddr > PHY_MAX_ADDR;
|
|
}
|
|
|
|
static int mvgbe_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!mvgbe_port_is_fixed_link(dmvgbe)) {
|
|
dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
|
|
dmvgbe->phy_interface,
|
|
dmvgbe->phyaddr);
|
|
if (!dmvgbe->phydev)
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvgbe_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
|
|
return __mvgbe_send(dmvgbe, packet, length);
|
|
}
|
|
|
|
static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
|
|
return __mvgbe_recv(dmvgbe, packetp);
|
|
}
|
|
|
|
static void mvgbe_stop(struct udevice *dev)
|
|
{
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
|
|
__mvgbe_halt(dmvgbe);
|
|
}
|
|
|
|
static int mvgbe_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
struct mii_dev *bus;
|
|
int ret;
|
|
|
|
ret = mvgbe_alloc_buffers(dmvgbe);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dmvgbe->regs = (void __iomem *)pdata->iobase;
|
|
|
|
bus = mdio_alloc();
|
|
if (!bus) {
|
|
printf("Failed to allocate MDIO bus\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
bus->read = smi_reg_read;
|
|
bus->write = smi_reg_write;
|
|
snprintf(bus->name, sizeof(bus->name), dev->name);
|
|
bus->priv = dmvgbe;
|
|
dmvgbe->bus = bus;
|
|
|
|
ret = mdio_register(bus);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops mvgbe_ops = {
|
|
.start = mvgbe_start,
|
|
.send = mvgbe_send,
|
|
.recv = mvgbe_recv,
|
|
.stop = mvgbe_stop,
|
|
.write_hwaddr = mvgbe_write_hwaddr,
|
|
};
|
|
|
|
static int mvgbe_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
|
|
void *blob = (void *)gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
int fl_node;
|
|
int pnode;
|
|
unsigned long addr;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
pdata->phy_interface = -1;
|
|
|
|
pnode = fdt_node_offset_by_compatible(blob, node,
|
|
"marvell,kirkwood-eth-port");
|
|
|
|
/* Get phy-mode / phy_interface from DT */
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
|
|
|
|
dmvgbe->phy_interface = pdata->phy_interface;
|
|
|
|
/* fetch 'fixed-link' property */
|
|
fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
|
|
if (fl_node != -FDT_ERR_NOTFOUND) {
|
|
/* set phy_addr to invalid value for fixed link */
|
|
dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
|
|
dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
|
|
dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
|
|
} else {
|
|
/* Now read phyaddr from DT */
|
|
addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
|
|
if (addr > 0)
|
|
dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mvgbe_ids[] = {
|
|
{ .compatible = "marvell,kirkwood-eth" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(mvgbe) = {
|
|
.name = "mvgbe",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mvgbe_ids,
|
|
.of_to_plat = mvgbe_of_to_plat,
|
|
.probe = mvgbe_probe,
|
|
.ops = &mvgbe_ops,
|
|
.priv_auto = sizeof(struct mvgbe_device),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|