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u-boot/drivers/ddr/fsl
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York Sun 56848428a8 drivers/ddr/fsl: Adjust bstopre value 
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
..
arm_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ctrl_regs.c driver/ddr/fsl: Fix driver to support empty first slot 2015-04-23 08:55:53 -07:00
ddr1_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr2_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr3_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr4_dimm_params.c driver/ddr/fsl: Fix driver to support empty first slot 2015-04-23 08:55:53 -07:00
fsl_ddr_gen4.c driver/ddr/fsl: Add workaround for DDR erratum A008511 2015-04-23 08:55:54 -07:00
interactive.c driver/ddr/fsl: Fix driver to support empty first slot 2015-04-23 08:55:53 -07:00
lc_common_dimm_params.c driver/ddr/fsl: Fix driver to support empty first slot 2015-04-23 08:55:53 -07:00
main.c drivers/ddr/fsl: Adjust bstopre value 2015-08-03 12:06:38 -07:00
Makefile driver/ddr/fsl: Add DDR4 support to Freescale DDR driver 2014-04-22 17:58:48 -07:00
mpc85xx_ddr_gen1.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
mpc86xx_ddr.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
options.c drivers/ddr/fsl: Adjust bstopre value 2015-08-03 12:06:38 -07:00
util.c drivers/ddr/fsl: Update DDR driver for DDR4 2015-04-23 08:55:53 -07:00