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Dinh Nguyen c624d07f3f arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines 
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-03 17:32:16 +01:00
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mach arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines 2015-11-03 17:32:16 +01:00