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Currently this pinctrl driver only supports BLSP UART2 specific pin configuration. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm QCS404 pinctrl
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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#include "pinctrl-snapdragon.h"
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#include <common.h>
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#define MAX_PIN_NAME_LEN 32
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static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
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static const char * const msm_pinctrl_pins[] = {
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"SDC1_RCLK",
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"SDC1_CLK",
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"SDC1_CMD",
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"SDC1_DATA",
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"SDC2_CLK",
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"SDC2_CMD",
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"SDC2_DATA",
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};
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static const struct pinctrl_function msm_pinctrl_functions[] = {
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{"blsp_uart2", 1},
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};
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static const char *qcs404_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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return msm_pinctrl_functions[selector].name;
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}
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static const char *qcs404_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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if (selector < 120) {
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snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
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return pin_name;
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} else {
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return msm_pinctrl_pins[selector - 120];
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}
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}
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static unsigned int qcs404_get_function_mux(unsigned int selector)
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{
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return msm_pinctrl_functions[selector].val;
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}
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struct msm_pinctrl_data qcs404_data = {
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.pin_count = 126,
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.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
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.get_function_name = qcs404_get_function_name,
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.get_function_mux = qcs404_get_function_mux,
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.get_pin_name = qcs404_get_pin_name,
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};
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