mirror of
https://github.com/AsahiLinux/u-boot
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ff36fd8591
add support for the AMD db1550 board * Patch by Travis Sawyer, 15 Sep 2004: Add CONFIG_SERIAL_MULTI support for ppc4xx, update README.serial_multi
224 lines
6.4 KiB
C
224 lines
6.4 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file contains the configuration parameters for the dbau1x00 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_DBAU1X00 1
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#define CONFIG_AU1X00 1 /* alchemy series cpu */
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#ifdef CONFIG_DBAU1000
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/* Also known as Merlot */
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#define CONFIG_AU1000 1
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#else
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#ifdef CONFIG_DBAU1100
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#define CONFIG_AU1100 1
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#else
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#ifdef CONFIG_DBAU1500
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#define CONFIG_AU1500 1
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#else
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#ifdef CONFIG_DBAU1550
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/* Cabernet */
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#define CONFIG_AU1550 1
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#else
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#error "No valid board set"
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#endif
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#endif
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#endif
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#endif
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#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
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#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
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#define CONFIG_BAUDRATE 115200
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"addmisc=setenv bootargs $(bootargs) " \
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"console=ttyS0,$(baudrate) " \
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"panic=1\0" \
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"bootfile=/tftpboot/vmlinux.srec\0" \
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"load=tftp 80500000 $(u-boot)\0" \
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""
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#ifdef CONFIG_DBAU1550
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/* Boot from flash by default, revert to bootp */
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#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
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~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
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CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
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CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
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#else /* CONFIG_DBAU1550 */
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/* Boot from Compact flash partition 2 as default */
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#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm"
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
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~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
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CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
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CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
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#endif /* CONFIG_DBAU1550 */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args*/
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#define CFG_MALLOC_LEN 128*1024
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#define CFG_BOOTPARAMS_LEN 128*1024
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#define CFG_MHZ 396
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#if (CFG_MHZ % 12) != 0
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#error "Invalid CPU frequency - must be multiple of 12!"
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#endif
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#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
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#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CFG_LOAD_ADDR 0x81000000 /* default load address */
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#define CFG_MEMTEST_START 0x80100000
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#define CFG_MEMTEST_END 0x80800000
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#ifdef CONFIG_DBAU1550
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
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#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
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#else /* CONFIG_DBAU1550 */
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
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#endif /* CONFIG_DBAU1550 */
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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/* The following #defines are needed to get flash environment right */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10)
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#define CFG_INIT_SP_OFFSET 0x400000
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/* We boot from this flash, selected with dip switch */
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#define CFG_FLASH_BASE PHYS_FLASH_2
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_NOWHERE 1
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/* Address and size of Primary Environment Sector */
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#define CFG_ENV_ADDR 0xB0030000
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#define CFG_ENV_SIZE 0x10000
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#define CONFIG_FLASH_16BIT
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_NET_MULTI
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#ifdef CONFIG_DBAU1550
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#define MEM_SIZE 192
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#else
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#define MEM_SIZE 64
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#endif
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#define CONFIG_MEMSIZE_IN_BYTES
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#ifndef CONFIG_DBAU1550
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/*---ATA PCMCIA ------------------------------------*/
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#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
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#define CFG_PCMCIA_MEM_ADDR 0x20000000
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#define CONFIG_PCMCIA_SLOT_A
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#define CONFIG_ATAPI 1
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#define CONFIG_MAC_PARTITION 1
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/* We run CF in "true ide" mode or a harddrive via pcmcia */
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#define CONFIG_IDE_PCMCIA 1
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/* We only support one slot for now */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET 8
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET 0
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0100
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#endif /* CONFIG_DBAU1550 */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384
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#define CFG_ICACHE_SIZE 16384
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#define CFG_CACHELINE_SIZE 32
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#endif /* __CONFIG_H */
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