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c0a4e6b889
Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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| .. | ||
| fsl_pci_init.c | ||
| Makefile | ||
| pci.c | ||
| pci_auto.c | ||
| pci_ftpci100.c | ||
| pci_ftpci100.h | ||
| pci_indirect.c | ||
| pci_ixp.c | ||
| pci_sh4.c | ||
| pci_sh7751.c | ||
| pci_sh7780.c | ||
| tsi108_pci.c | ||
| w83c553f.c | ||