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https://github.com/AsahiLinux/u-boot
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55ca747f66
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
92 lines
1.4 KiB
C
92 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <asm/cache.h>
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#include <dm/uclass-internal.h>
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#include <cache.h>
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#include <asm/csr.h>
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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/* mcctlcommand */
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#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
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/* D-cache operation */
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#define CCTL_L1D_WBINVAL_ALL 6
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#endif
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#endif
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#ifdef CONFIG_V5L2_CACHE
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static void _cache_enable(void)
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{
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struct udevice *dev = NULL;
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uclass_find_first_device(UCLASS_CACHE, &dev);
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if (dev)
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cache_enable(dev);
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}
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static void _cache_disable(void)
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{
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struct udevice *dev = NULL;
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uclass_find_first_device(UCLASS_CACHE, &dev);
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if (dev)
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cache_disable(dev);
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}
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#endif
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void flush_dcache_all(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
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#endif
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#endif
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#endif
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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int dcache_status(void)
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{
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return 0;
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}
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