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https://github.com/AsahiLinux/u-boot
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d8a146d19b
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] bd7ef41398
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
31 lines
848 B
C
31 lines
848 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Andes Technology Corporation
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*/
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#ifndef _ASM_ANDES_CSR_H
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#define _ASM_ANDES_CSR_H
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#include <asm/asm.h>
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#include <linux/const.h>
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MMISC_CTL 0x7d0
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#define CSR_MARCHID 0xf12
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#define CSR_MCCTLCOMMAND 0x7cc
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#define MCACHE_CTL_IC_EN_OFFSET 0
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#define MCACHE_CTL_DC_EN_OFFSET 1
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_DC_COHEN_OFFSET 19
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#define MCACHE_CTL_DC_COHSTA_OFFSET 20
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#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
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#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
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#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
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#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
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#define CCTL_L1D_WBINVAL_ALL 6
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#endif /* _ASM_ANDES_CSR_H */
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